Exploiting program-level masking and error propagation for constrained reliability optimization

Shafique, Muhammad; Rehman, Semeen; Aceituno, Pau Vilimelis; Henkel, Jörg

doi:10.1145/2463209.2488755

Cited by 62 publications

(31 citation statements)

References 22 publications

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“…To evaluate the variable vulnerabilities to soft error, several important factors should be taken into account, including lifetime, functional dependencies, weight in conditional branches and error masking effects [12,14,15,16]. The work in [12,14,15] did not consider the important error masking phenomena, especially for the relational and logic operations which are common in CFI designs.…”

Section: Vulnerability Analysismentioning

confidence: 99%

“…The work in [12,14,15] did not consider the important error masking phenomena, especially for the relational and logic operations which are common in CFI designs. The authors in [16] considered only the data flow errors and used path enumeration to exploit program-level error propagation and masking mechanisms. However, path enumeration is not applicable for CFI designs, as not only the number of paths grow exponentially with the number of branch nodes, but also the presence of loops makes this enumeration intractable.…”

Section: Vulnerability Analysismentioning

confidence: 99%

“…one AND operation can theoretically mask half of the input errors with P mask = 0.5 and generate the correct output). Note that for different operation types P mask can be different, and in this work we adopt the masking probability values from [16]. When the errors propagate to the conditional IF branch (i.e.…”

Section: Error Propagation Modelingmentioning

confidence: 99%

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Reliability-aware Register Binding for Control-Flow Intensive Designs

Chen

Tahoori

2014

Proceedings of the 51st Annual Design Automation Conference

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As soft error is a major reliability issue for nanoscale VLSI, addressing it during high level synthesis can have a significant impact on the overall design quality. Motivated by the observation that for behavioral designs, especially control-flow intensive ones, variables have nonuniform soft error vulnerabilities, we propose a novel reliability-aware register binding technique to explore more effective soft error mitigation during high level synthesis. We first perform a comprehensive variable vulnerability analysis at the behavioral level, by considering error propagation and masking in both control and data flow. Then an optimization based on integer linear programming is used to incorporate vulnerabilities into the register binding phase with a selective register protection scheme. The experimental results reveal that the proposed technique can achieve significant soft error mitigation (60% coverage of the total vulnerabilities) with a small portion (20%) of register protection.

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Section: Vulnerability Analysismentioning

confidence: 99%

Section: Vulnerability Analysismentioning

confidence: 99%

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Reliability-aware Register Binding for Control-Flow Intensive Designs

Chen

Tahoori

2014

Proceedings of the 51st Annual Design Automation Conference

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“…However, all the existing works focus on approximating different components such as procedure approximation, input data approximation, control-flow based approximation etc. [4,27]. Other works have studied the errorresilience of data in architectural components such as the arithmetic units, register files, etc.…”

Section: Overviewmentioning

confidence: 99%

“…This may be easily accomplished for small programs, but is difficult or infeasible for complex programs and legacy softwares. Other works have shown that program approximations can be achieved through algorithmic choices, runtime decision making frameworks, and on the architectural or device level [1,2,6,27]. The provision of algorithmic choices too is the programmer's responsibility and the application is compiled using all the versions of a procedure.…”

Section: Introductionmentioning

confidence: 99%

Asac

Roy

Ray

Wang

et al. 2014

Proceedings of the 2014 SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems

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The approximation based programming paradigm is especially attractive for developing error-resilient applications, targeting low power embedded devices. It allows for program data to be computed and stored approximately for better energy efficiency. The duration of battery in the smartphones, tablets, etc. is generally more of a concern to users than an application's accuracy or fidelity beyond certain acceptable quality of service. Therefore, relaxing accuracy to improve energy efficiency is an attractive tradeoff when permissible by the application's domain. Recent works suggest source code annotations and type qualifiers to facilitate safe approximate computation and data manipulation. It requires rewriting of programs or the availability of source codes for annotations. This may not be feasible as real-world applications tend to be large, with source code that is not readily available.In this paper, we propose a novel sensitivity analysis that automatically generates annotations for programs for the purpose of approximate computing. Our framework, ASAC, extracts information about the sensitivity of the output with respect to program data. We show that the program output is sensitive to only a subset of program data that we deem critical, and hence must be precise. The rest of the data can be computed and stored approximately. We evaluated our analysis on a range of applications, and achieved a 86% accuracy compared to manual annotations by programmers. We validated our analysis by showing that the applications are within the acceptable QoS threshold if we approximate the non-critical data.

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RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

Herkersdorf

Engel

Glaß

et al. 2020

Dependable Embedded Systems

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The Resilience Articulation Point (RAP) model aims to provision a probabilistic fault abstraction and error propagation concept for various forms of variability related faults in deep sub-micron CMOS technologies at the semiconductor material or device levels. RAP assumes that each of such physical faults will eventually manifest as a single- or multi-bit binary signal inversion or out-of-specification delay in a signal transition between bit values. When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, finite state machine (FSM) states, IP macro-interfaces, or software variables. Thus, design concerns can be investigated at higher abstraction layers without the necessity to further consider the full details of lower levels of design. This chapter introduces the ideas of RAP based on examples of particle strike, noise and voltage drop induced bit errors in SRAM cells. Furthermore, we show by different examples how probabilistic bit flips are systematically abstracted and propagated towards instruction and data vulnerability at MPSoC architecture level, and how RAP can be applied for dynamic testing and application-level optimizations in an autonomous robot scenario.

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Exploiting program-level masking and error propagation for constrained reliability optimization

Cited by 62 publications

References 22 publications

Reliability-aware Register Binding for Control-Flow Intensive Designs

Reliability-aware Register Binding for Control-Flow Intensive Designs

Asac

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

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