Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC Deblocking Filter

“…The algorithm is based on congestion negotiation and simulated annealing methods. Starting from an invalid schedule that overuses resources, it tries to reduce overuse over time until a valid schedule is found [11]. One main advantage of the DRESC framework is its flexibility: the tools are designed to be retargetable within the ADRES template.…”

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays

“…In essence, the DRESC tool performs the tasks of scheduling, placement, and routing simultaneously. An example from [16] illustrates the scheduling problem, and provides insight into the interconnect requirements in the reconfigurable fabric. Consider the implementation of the dataflow graph in Figure 2(a) on the fabric of Figure 2(b).…”

“…In this example, the instruction executed by each CFU does not change over time, thus, one context is sufficient for storing the configuration of each multiplexer and functional unit control bits. In general, an architecture with II contexts are required to implement a schedule [16], where a context is a complete set of configuration bits needed to store the values of all multiplexer and functional unit select lines in the fabric. DRESC begins the scheduling task by attempting to schedule the dataflow graph on an architecture with II=1.…”

“…The IMPACT tool is used as a front-end to parse C code, do some optimization and analysis, and emit a data-flow graph [17]. Highly parallelizable loops within the code are then identified, and the DRESC tool uses a modulo-scheduling algorithm to schedule each loop on the target architecture, assigning each operation in the loop to a specific CFU and a specific time slice [16]. The DRESC tool takes into account the characteristics of the target architecture, including the capabilities of each CFU and the interconnect between the CFU's; this ensures that the resulting schedule can be implemented on the reconfigurable device.…”

“…ADRES consists of a VLIW processor tightly coupled to a reconfigurable fabric containing a heterogeneous grid of CFU's. Section 2 contains a description of the ADRES architecture, as well as the DRESC tool which maps programs to the device [16]. Section 3 will describe the interconnect architectures we considered, and Section 4 will evaluate these architectures experimentally.…”