Architecture for Dynamically Reconfigurable Embedded Systems (ADRES) is a templatized coarsegrained reconfigurable processor architecture. It targets at embedded applications which demand highperformance, low-power and high-level language programmability. Compared with typical very long instruction word-based digital signal processor, ADRES can exploit higher parallelism by using more scalable hardware with support of novel compilation techniques. We developed a complete tool-chain, including compiler, simulator and HDL generator. This paper describes the design case of a media processor targeting at H.264 decoder and other video tasks based on the ADRES template. The whole processor design, hardware implementaiton and application mapping are done in a relative short period. Yet we obtain C-programmed real-time H.264/AVC CIF decoding at 50 MHz. The die size, clock speed and the power consumption are also very competitive compared with other processors.
A tremendous number of devices, a limitation of wiring, and very low power dissipation density are design constraints of future nanoelectronic circuits composed of quantum-effect devices. Furthermore, functional integration, which is the possibility of exploiting quantum effects to obtain a function specific behavior, becomes a core design principle. This paper analyzes the effect of this technological progress on the design of nanoelectronic circuits and describes computational paradigms revealing novel features such as distributed storage, fault tolerance, selforganization, and local processing. In particular, linear threshold networks, the associative matrix, self-organizing feature maps, and cellular arrays are investigated from the viewpoint of their potential significance for nanoelectronics. Although these concepts have already been implemented using present technologies, the intention of this paper is to give an impression of their usefulness to system implementations with quantum-effect devices.
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