Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines

Kar, Monodeep; Singh, Arvind; Mathew, Sanu; Rajan, Anand Prem; De, Vivek; Mukhopadhyay, Saibal

doi:10.1145/2934583.2934607

Cited by 23 publications

(6 citation statements)

References 92 publications

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“…Note that the total system current will also include the CPU current. However, the adversary can filter out the high frequency components of the total current by applying signal processing [47] since the CPU current frequency is much higher compared to cache current (long NVM read and write latency); (ii) the proposed SCA model is independent of cache size. This assumption is true as long as the cache is large enough to hold the round keys.…”

Section: Assumptions Used In This Workmentioning

confidence: 99%

Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories

Khan

Bhasin

Liu

et al. 2021

JLPEA

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Emerging Non-Volatile Memories (NVMs) such as Magnetic RAM (MRAM), Spin-Transfer Torque RAM (STTRAM), Phase Change Memory (PCM) and Resistive RAM (RRAM) are very promising due to their low (static) power operation, high scalability and high performance. However, these memories bring new threats to data security. In this paper, we investigate their vulnerability against Side Channel Attack (SCA). We assume that the adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. First, we show our analysis of simulation results. Then, we use commercial NVM chips to validate the analysis. We also investigate the effectiveness of encoding against SCA on emerging NVMs. Finally, we summarize two new flavors of NVMs that can be resilient against SCA. To the best of our knowledge, this is the first attempt to do a comprehensive study of SCA vulnerability of the majority of emerging NVM-based cache.

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Section: Assumptions Used In This Workmentioning

confidence: 99%

Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories

Khan

Bhasin

Liu

et al. 2021

JLPEA

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“…There are several strategies to countermeasure DPA, some of these strategies are: transistor disposition [10], encoding scheme [11], buck-voltage regulators [12], switching capacitors [13], and passive elements [14]. Several strategies to minimize the information leaked on CMOS circuits rely on different logic styles to balance the combinational computations and electrical properties.…”

Section: B Circuit-level Countermeasuresmentioning

confidence: 99%

Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing

Lima

Paim

Wuerdig

et al. 2020

JICS

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Differential power analysis (DPA) exploits the difference between the instantaneous power of the circuit arches transitions to stole the state as information aiming to unveil the cryptographic key. Secure triple track logic (STTL) is a circuit-level countermeasure to DPA attacks based on dual-rail precharge logic (DPL). STTL is robust to attacks due to the delay in an insensitive feature that mitigates the logic glitches generated by the different path delays that lead to the logic gate inputs until they stabilize. The main STTL drawback, however, is the asymmetry of the transistor topology. Asymmetry causes unbalanced internal capacitances and different internal paths for the current flow, and DPA exploits it as a source of information leakage. Our work proposes three circuit topologies, combining multi-Vt transistors with a circuit counterbalancing strategy, aiming to improve the STTL DPA attack-resistance. Data encryption standard substitution-box circuit, designed in a TSMC 40 nm CMOS process, is our application case study to evaluate the DPA attack-resistance. Results gathered at the application-level show that our proposals outperform DPA attack-resistance of the prior work.

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“…2 On-chip VR as a countermeasure against VGA In [30,31,32,33,34,35] an on-chip VR is used as the first defense mechanism against power and EM attacks that motivates the use of a VR as a defense mechanism against fault injection by a power supply channel. Implicitly VRs are utilized as triumphant countermeasures to tackle power and EM attacks; however, their vulnerabilities to fault attacks require an investigation.…”

Section: Fault Analysismentioning

confidence: 99%

Voltage regulator assisted lightweight countermeasure against fault injection attacks

Vosoughi¹,

Wang²,

Köse³

2020

Preprint

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The impeccable design of sensitive and cryptographic circuits (CC) against fault injection attacks is essential for modern data storage, communication, and computation systems that are susceptible to fault injection attacks. The robustness of a CC against voltage glitch attacks increases with an on-chip voltage regulator that considers the impact of topology and component selection on the fault injection robustness. With an emphasis on increasing the number of phases in a multiphase voltage regulator and component selection, an on-chip voltage regulator with multiphase configuration and an optimal operating point is proposed as a lightweight countermeasure to minimize injected glitches. Furthermore, an infective countermeasure is added to the on-chip multiphase voltage regulator that contaminates the computation of the cryptographic algorithm when a voltage glitch reaches to the CC. By increasing the number of phases from 1 to 16, the confrontation with fault attacks increases by 52.45%, which is equal to 91.82% if the number of phases increases to 32. Using the infective countermeasure for fault resiliency, the security-enhanced CC provides a robust and resilient solution against fault attacks that improve the security and availability of the device. Keywords voltage regulator • multiphase voltage regulator • fault injection attack • side-channel analysis • countermeasures • power glitches • infective computation • fault resilient computation

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Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines

Abstract: To my parents, Chirasree Kar and Nirmal Kar.

Cited by 23 publications

References 92 publications

Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories

Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories

Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing

Voltage regulator assisted lightweight countermeasure against fault injection attacks

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