Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing

Abstract

Differential power analysis (DPA) exploits the difference between the instantaneous power of the circuit arches transitions to stole the state as information aiming to unveil the cryptographic key. Secure triple track logic (STTL) is a circuit-level countermeasure to DPA attacks based on dual-rail precharge logic (DPL). STTL is robust to attacks due to the delay in an insensitive feature that mitigates the logic glitches generated by the different path delays that lead to the logic gate inputs until they stabilize. The main STTL drawback, however, is the asymmetry of the transistor topology. Asymmetry causes unbalanced internal capacitances and different internal paths for the current flow, and DPA exploits it as a source of information leakage. Our work proposes three circuit topologies, combining multi-Vt transistors with a circuit counterbalancing strategy, aiming to improve the STTL DPA attack-resistance. Data encryption standard substitution-box circuit, designed in a TSMC 40 nm CMOS process, is our application case study to evaluate the DPA attack-resistance. Results gathered at the application-level show that our proposals outperform DPA attack-resistance of the prior work.

Hardware Countermeasures against Power Analysis Attacks: a Survey from Past to Present

“…Multi-Threshold Balanced Secure Triple Track Logic (MT-BSTTL) is the first topology to use multi-V t on power attacks purpose. MT-BSTTL implements multi-V t and capacitance balancing techniques to minimize the limitations of STTL [24]. Dual-spacer Dual-rail Delay-insensitive Logic -(D 3 L) proposed by Cilio [25] is a DPL based on asynchronous circuits able to mitigate capacitive unbalances between the dual rails using a dual-spacer protocol to decouple the data correlation with power dissipation during the computation.…”