Experimental measurement of a novel power gating structure with intermediate power saving mode

Kim, Suhwan; Kosonocky, Stephen; Knebel, D.R.; Stawiasz, K.

doi:10.1145/1013235.1013246

Cited by 49 publications

(31 citation statements)

References 16 publications

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“…We have implemented the proposed circuit and the conventional circuit [6] with 180 nm SOI technology. The supply voltage is 1.8 V. We have employed a benchmark circuit cm82a from the MCNC benchmark circuits.…”

Section: Implementation and Simulation Resultsmentioning

confidence: 99%

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A novel power gating scheme with charge recycling

Tada

Notani

Numa

2006

IEICE Electron. Express

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Abstract:In MTCMOS, the circuit state should be preserved for state retentive sleep, and the virtual power/ground rails clamp (VRC) scheme is an effective method for this purpose. Our approach realizes the voltage clamp function without additional devices like diodes, by feeding the virtual ground voltage back into a sleep signal. There are also other effects; cutting off the leak current of the sleep buffer, and charge recycling of sleep signal node. We have achieved a 19.7% lower power consumption and a 5.4% cell area reduction.

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Section: Implementation and Simulation Resultsmentioning

confidence: 99%

“…Kim et al [6] have proposed a new VRC scheme with a pMOS transistor as the diode. They implemented state retentive and non-state retentive modes by controlling the pMOS diode input.…”

Section: Virtual Power/ground Rails Clamp (Vrc) Schemementioning

confidence: 99%

A novel power gating scheme with charge recycling

Tada

Notani

Numa

2006

IEICE Electron. Express

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“…Sleepy Transistor [5], Sleepy Stack [6], DRG Cache [7], Gated V DD [8], Sleepy Keeper [9], Multiple Power Gating [10], VCLEARIT [11] are some of the circuit level techniques for low leak operation. Different multi V TH techniques for low leak operations discussed in literature are Dual threshold CMOS [12] Variable threshold CMOS (VTMOS) [13].…”

Section: (V Gs -V T )/ (Nv T ) [1-e (-V Ds / V T ) ]mentioning

confidence: 99%

“…As has been concluded in this reference this circuit methodology has resulted in large dynamic power dissipation. Multiple power gating method of [10] retains the state but has large associated power consumption. VCLEARIT technique reduces power during sleep mode but results in to large dynamic power dissipation.…”

Section: Iiperformance Analysis Of Earlier Leakage Reduction Techniquesmentioning

confidence: 99%

Novel Low Power Logic Gates using Sleepy Techniques

Kalal¹,

I²,

Pawar³

2015

IJAREEIE

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ABSTRACT:The subthreshold voltage is declining in successive nanometre technologies and has an associated effect of enhanced leakage current. This causes the static (leakage) power to be a vital portion of total power dissipation in a VLSI circuit. Two novel circuit techniques for leakage current reduction in logic gates are presented in this work. The proposed circuit techniques are applied to universal NAND and NOR logic gates. The performance of these low leak gates is compared with earlier CMOS circuit leakage minimization techniques applied to these gates. The novel ultra low leak technique provides maximum leakage current reduction with lower output levels. Low Power State Retention-LPSR technique provides lower leakage power and the state of the gate can also be retained in sleep mode. The proposed low leak gates are designed and simulated using cadence design tools for 90 nm CMOS process technology. The leakage power for the novel methods during sleep mode is found to be better with and without state retention as compared to earlier best known techniques. The dynamic power dissipation for the proposed techniques is least. KEYWORDS:Leakage power, sleep transistor, power gating, total average power, state retention. I.INTRODUCTIONFor successive technology generations the transistor feature sizes are becoming smaller and the channel length is reducing. The threshold voltage and gate oxide thickness are also being scaled down [1] to maintain performance.The subthreshold voltage is going down to keep pace with reduced supply voltage for scaled down technologies in order to have good performance. The lower subthreshold voltage in nanometre technologies gives rise to enhanced leakage current because transistors cannot be switched off completely. Subthreshold current is the drain to source leakage current when the transistor is off. Leakage current acts as a limiting factor for further scaling down of transistors as per the International Roadmap for Semiconductor Technology (IRST) [2]. Thus it is essential to reduce leakage (static) power consumption during the idle or standby states of the circuits.When a CMOS circuit is active, the total power dissipation is due to dynamic and static components. In the inactive (standby) mode, the CMOS circuit dissipates power due to the standby leakage current [3] [4]. Sub-threshold leakage current for V GS < V T is given by2) In these equations I DSO is current at threshold dependent (on process and device geometry), V TO is the zero bias threshold voltage, γ -is the linearized body effect coefficient, η represents the effect of V DS on threshold voltage, n is the sub-threshold swing coefficient, V T is thermal voltage respectively. η term describes Drain Induced Barrier Lowering. Subthreshold conduction is enhanced by Drain Induced Barrier Lowering (DIBL) in which positive V DS effectively reduces V T . Leakage current doubles for every 8 0 to 10 0 K rise in temperature.The subthreshold leakage current can be reduced by increasing threshold voltage V TO , increasing source ...

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“…In real transistors current does not abruptly cut-off below threshold, but drops off exponentially as given by equation (1). This sub-threshold leakage current for V GS < V T is given by In these equations I DS0 is current at threshold( dependent on process and device geometry), V T0 is the zero bias threshold voltage, γ -is the linearized body effect coefficient, η represents the effect of V DS on threshold voltage, n is the sub- [4], Dual V T CMOS [5], DRG Cache [6], multiple power gating [7], sleepy keeper [8], VCLEART [9], LECTOR [10], GALLEOR [11], Sleepy Pass Gate [12], low leak stable SRAM [13], ultra low leak and state retention for inverters [14] , are some of the techniques for leakage reduction. Each method has its own merits and demerits.…”

Section: Introductionmentioning

confidence: 99%

LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design

Rajani¹,

Kulkarni²

2012

IJCA

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In mobile computing and mobile communication applications powered by battery, the battery life is a premier concern. Leakage power loss is critical in CMOS VLSI circuits as it leaks the battery even when devices are in idle state. To reduce subthreshold leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called LPSR Technique is proposed in this work. Earlier well known techniques for leakage reduction and state retention are compared with this technique. This technique reduces maximum amount of leakage power during deep sleep mode, maximum power reduction during dynamic (clocked) mode and has a provision of preserving state in low power sleep mode. All the circuits are designed, simulated and low power performance evaluation is done using 90nm CMOS technology files in Cadence Design Environment. General TermsCMOS VLSI Design, low power operation

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Experimental measurement of a novel power gating structure with intermediate power saving mode

Cited by 49 publications

References 16 publications

A novel power gating scheme with charge recycling

A novel power gating scheme with charge recycling

Novel Low Power Logic Gates using Sleepy Techniques

LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design

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