Experimental fault analysis of 1 Mb SRAM chips

Goto, Hideaki; Nakamura, Shōgo; Iwasaki, Kei

doi:10.1109/vtest.1997.599438

Cited by 13 publications

(9 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Increased power dissipation also leads to an increase in the temperature, which directly affects the reliability of the system. As reported in [5], the delay fault rate doubles for every 10°C increase in the operating temperature. A 10-15°C increase in the temperature can halve the life span of a circuit [15].…”

Section: Overviewsupporting

confidence: 53%

Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management

Prakash¹,

Koren²,

Krishna³

2013

Journal of Low Power Electronics

View full text Add to dashboard Cite

Section: Overviewsupporting

confidence: 53%

Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management

Prakash¹,

Koren²,

Krishna³

2013

Journal of Low Power Electronics

View full text Add to dashboard Cite

“…While the amount of temperature reduction seems to be insignificant at first sight, it actually can effectively reduce the fault rate of the entire chip, since the fault rate doubles for every 10°C increase in temperature [12]. Meanwhile, previous studies have shown that a large number of delay violations would occur if the peak temperature exceeds 85°C [4], [6]. It can be seen from the results that for most benchmarks, the proposed algorithm can effectively reduce the peak temperature to below 84°C.…”

Section: B Temperature Resultsmentioning

confidence: 98%

“…Researchers have built both analytical and experimental models for temperature-induced fault rate increases, such as delay violations [4], negative bias temperature instability [3], neutron-induced latchup [11], and on-chip interconnect [5]. A number of design and modelling challenges have been summarized in [12].…”

Section: Related Workmentioning

confidence: 99%

“…Negative bias temperature instability (NBTI) and hot carrier injection (HCI) furthermore cause violations of circuit timing constraints [3]. As reported in [4], delay fault rates double for each 10°C increase in temperature. Moreover, as every 20°C increase in temperature causes a 5-6% increase in Elmore delay in interconnects, clock skew problems become noticeable for temperature spatial variations of around 20°C and above [5].…”

Section: Introductionmentioning

confidence: 95%

See 1 more Smart Citation

Processor reliability enhancement through compiler-directed register file peak temperature reduction

Yang

Orailoğlu

2009

2009 IEEE/IFIP International Conference on Dependable Systems &Amp; Networks

View full text Add to dashboard Cite

Abstract-Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliability. Temperature hotspots not only accelerate the physical failure mechanisms such as electromigration and dielectric breakdown, but furthermore make the system more vulnerable to timing-related intermittent failures. Traditional thermal management techniques suffer from considerable performance overhead as the entire processor needs to be stalled or slowed down to preclude heat accumulation. Given the significant temporal and spatial variations of the chip-wide temperature, we propose in this paper a technique that directly targets one of the resources that is most likely to overheat in current processors, namely, the register files. Instead of duplicating or physically distributing the register file, we suggest to attain power density control through exploiting the extant spatial slack associated with register file accesses. Based on application-specific access profiles, a compiler-directed register shuffling strategy is proposed to deterministically construct the logical to physical register mapping in a rotating manner. Simulation results confirm that the proposed technique attains, within a limited hardware budget and negligible performance degradation, effective reduction in peak temperature and hence in the expected fault rates for the entire chip.

show abstract

“…An SC consists of a combination of values for the different stresses, for example, V DD = 4.5 V and Temp = 70º C. In previous work, researchers have performed base tests with up to 48 SCs, 5 reporting the results of testing 1,024, 128-Kbyte × 8 SRAM chips using a few tests. These results indicated that the fault coverage depended heavily on the stresses used, such as the load used on the output pins or the power supply voltage.…”

mentioning

confidence: 99%

Industrial evaluation of DRAM tests

Goor

Neef

1999

Proceedings of the Conference on Design, Automation and Test in Europe

View full text Add to dashboard Cite

IEEE Design & Test of ComputersDRAM PRODUCTION tests are currently necessary to reach a defect-per-million level that approaches the single-digit numbers. This implies that a single memory test is insufficient; rather, a set of tests is necessary. In addition, to obtain economically acceptable test times, test engineers must often manually optimize the test sets for the particular technology used. Consequently, researchers have devoted much time to designing memory tests optimized to detect a particular class of faults.1-4 These tests might have an academic origin or are based on Spice simulation, and possibly also on inductive fault analysis. The effectiveness of these tests remains a question.A test consists of a base test-an algorithm-applied using a particular stress combination (SC). An SC consists of a combination of values for the different stresses, for example, V DD = 4.5 V and Temp = 70º C. In previous work, researchers have performed base tests with up to 48 SCs,5 reporting the results of testing 1,024, 128-Kbyte × 8 SRAM chips using a few tests. These results indicated that the fault coverage depended heavily on the stresses used, such as the load used on the output pins or the power supply voltage. Earlier work applied a small set of march base tests, using many SCs, to 2-Kbyte × 8 SRAMs; this work also indicated that SCs were very important. Used base tests and stressesI describe the base tests and the stresses that compose an SC. I then give an overview of the tests built from the base tests and SCs. Base testsThe base tests we used for this set of experiments consisted of four classes: electrical, march, base cell, and repetitive. The number that follows each class name (in parentheses) is the number of base tests in that class.The notation for the base tests uses the following symbols:I ⇑ denotes an increasing address order (that is, address 0, 1, 2, and so on), I ⇓ denotes a decreasing address order, and I denotes that the test engineer can arbitrarily choose the address order to be ⇑ or ⇓.I list the required test time after the name of the base test; it is expressed as some function of n, the number of memory words. It can also rely on the settling time, t s = 5 ms. Class 1: Electrical tests (11).The class of electrical base tests consists of checks for contact (1), DC parameters (7), and AC parameters (3). An Industrial Evaluation of DRAM TestsThis application of 40 well-known memory tests to 1,896 1-Mbyte × 4 DRAM chips, used up to 48 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests-those covering more different functional faultsalso have higher fault coverage.

show abstract

Experimental fault analysis of 1 Mb SRAM chips

Cited by 13 publications

References 12 publications

Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management

Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management

Processor reliability enhancement through compiler-directed register file peak temperature reduction

Industrial evaluation of DRAM tests

Contact Info

Product

Resources

About