Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's

Majima, H.; Ishikuro, Hiroki; Hiramoto, Toshiro

doi:10.1109/55.852962

Cited by 93 publications

(68 citation statements)

References 9 publications

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“…The threshold voltage for each case was extracted from the simulation data using the derivative of g m /I D method [12], minimizing the effect of gate-voltage dependent mobility and series-resistance. Quantum confinement was found to upshift the threshold voltage by 45 mV, a similar trend to the inversion-mode devices due to the higher quantized subband energies [13,14], and degrade the drain current, as shown in Fig. 8, from 8% in strong accumulation (V GS = 1.300 V) to 90% in the subthreshold region (V GS = 0.200 V).…”

Section: Tcad Sentaurus Device Simulation Of Gaa Deeply Scaled Si Nansupporting

confidence: 55%

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Najmzadeh¹,

Bouvet²,

Grabinski³

et al. 2012

Solid-State Electronics

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a b s t r a c tIn this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve P2.5 GPa uniaxial tensile stress in the Si nanowire is reported. The deeply scaled Si nanowire including such uniaxial tensile stress shows a low-field electron mobility of 332 cm 2 /V s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to %400 K and a V TH drift of À1.72 mV/K and an ionized impurity scattering-based mobility reduction were observed.

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Section: Tcad Sentaurus Device Simulation Of Gaa Deeply Scaled Si Nansupporting

confidence: 55%

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Najmzadeh¹,

Bouvet²,

Grabinski³

et al. 2012

Solid-State Electronics

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“…This can also be deduced from the scatter of the experimental data from Ref. [97]. The simulation results of the transfer characteristics with a single impurity present in different regions in the channel of the device, shown in the left panel of Fig.…”

Section: Threshold Voltage Fluctuations Due To Unintentional Doping Imentioning

confidence: 80%

“…On top of the SOI layer sits gate-oxide layer, the thickness of which is 34 nm. This is rather thick gate oxide, but it is used to compare the simulation results with the experimental data of Majima et al [97]. The doping of the source/drain junctions equals 10 19 cm -3 (if not stated otherwise), and the gate is assumed to be a metal gate with workfunction equal to the semiconductor affinity.…”

Section: Threshold Voltage Fluctuations Due To Unintentional Doping Imentioning

confidence: 99%

Quantum and Coulomb Effects in Nano Devices

Vasileska¹,

Khan²,

Ahmed³

et al. 2011

Nano-Electronic Devices

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In state of the art devices, it is well known that quantum and Coulomb effects play significant role on the device operation. In this paper we demonstrate that a novel effective potential approach in conjunction with a Monte Carlo device simulation scheme can accurately capture the quantummechanical size quantization effects. We also demonstrate, via proper treatment of the short-range Coulomb interactions, that there will be significant variation in device design parameters for devices fabricated on the same chip due to the presence of unintentional dopant atoms at random locations within the channel.

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“…3 shows the second derivative of the total electron density per unit length (d 2 N t /dV 2 GS ) versus V GS for the GAA 15 nm wide Si NW MOSFETs for three channel doping concentrations, considering classical and quantum effects. The results reported in Table I show that the quantization is upshifting both the threshold and the flat-band voltages, due to the higher quantized subband energies [9], [23], [24]. Note that, even for the heavily doped structure and on the contrary to the IM devices [19], there is no hump effect below the gate voltage corresponding to the main peak in the d 2 N t /dV 2 GS versus V GS curve, thus representing a unique threshold voltage in the system.…”

Section: Gate-channel Capacitance and Effective Channel Widthmentioning

confidence: 99%

Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

Najmzadeh

Sallèse

Berthomé

et al. 2012

IEEE Trans. Electron Devices

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Abstract-In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deplete more electrons than the flat sides or the channel center, when above (local accumulation) and below (local depletion) the flat-band voltage, respectively. On the contrary to the corner effect in the inversion mode (IM) devices, there is no major contribution of corners in the subthreshold current, and therefore, there is no subthreshold device behavior degradation (only one threshold voltage in the system). N-type channel doping levels of 1 × 10 19 , 5 × 10 18 , and 1 × 10 18 cm −3 were used for quasi-stationary device simulations of JL and AM MOSFETs, and corner effect was studied for 5, 10, and 15 nm wide equilateral triangular Si NW MOSFETs with a 2 nm SiO 2 gate oxide thickness (V DS = 0 V; T = 300 K). While the local quantum and classical electron density peaks are located in the corner regions above the flat-band voltage, reducing the channel doping and the channel cross-section was found to slightly suppress the normalized total accumulation electron density per unit length, N acc t /(CW eff ), in strong accumulation regime.

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Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's

Cited by 93 publications

References 9 publications

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Quantum and Coulomb Effects in Nano Devices

Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

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