Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices

Salvo, B. De; Ghibaudo, G.; Pananakakis, G.; Masson, Pascal Le; Baron, T.; Buffet, N.; Fernandes, A.J.S.; Guillaumot, B.

doi:10.1109/16.936709

Cited by 142 publications

(73 citation statements)

References 48 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…By low-energy Si + ion implantation into thin SiO 2 layers on (001)Si, NCs of Si were formed a few nanometers above the Si/SiO 2 interface [3]. This allows charging of the NCs by direct electron tunneling, which is a prerequisite for high endurance and low operation voltages [6]. Further optimization of location and size of ion beam synthesized NCs for memory application requires a deeper understanding of the mechanisms involved, which determine (i) the built-up of Si supersaturation by high-fluence ion implantation and (ii) NC formation by phase separation.…”

mentioning

confidence: 99%

“…Additionally, the distance of the NCs from the interface is small enough to allow their charging by direct electron tunneling. This self-alignment of NCs as well as their degradation free charging/decharging is crucial for application in nonvolatile memories [6]. Varying ion implantation energy and annealing temperature gives additional control over the width of the depleted zone and the NC size, which will be described elsewhere [16].…”

mentioning

confidence: 99%

See 1 more Smart Citation

Size and location control of Si nanocrystals at ion beam synthesis in thin SiO2 films

Mueller

Heinig

Moeller

2002

Applied Physics Letters

View full text Add to dashboard Cite

Binary collision simulations of high-fluence 1 keV Si + ion implantation into 8 nm thick SiO 2 films on (001)Si were combined with kinetic Monte Carlo simulations of Si nanocrystal (NC) formation by phase separation during annealing. For nonvolatile memory applications, these simulations help to control size and location of NCs. For low concentrations of implanted Si, NCs form via nucleation, growth and Ostwald ripening, whereas for high concentrations Si separates by spinodal decomposition. In both regimes, NCs form above a thin NC free oxide layer at the SiO 2 /Si interface. This, self-adjusted layer has just a thickness appropriate for NC charging by direct electron tunneling. Only in the nucleation regime the width of the tunneling oxide and the mean NC diameter remain constant during a long annealing period. This behavior originates from the competition of Ostwald ripening and Si loss to the Si/SiO 2 interface. The process simulations predict that, for nonvolatile memories, the technological demands on NC synthesis are fulfilled best in the nucleation regime.Recently, nonvolatile memory concepts based on nanocrystals (NCs) embedded in the gate oxide of MOS transistors have attracted much interest [1]. For that aim, NCs have been synthesized by a variety of techniques like chemical vapor deposition [2], ion implantation [3,4], and Si aerosol deposition [5]. Ion implantation followed by thermally activated precipitation of the implanted impurity atoms is most compatible with current silicon technology. By low-energy Si + ion implantation into thin SiO 2 layers on (001)Si, NCs of Si were formed a few nanometers above the Si/SiO 2 interface [3]. This allows charging of the NCs by direct electron tunneling, which is a prerequisite for high endurance and low operation voltages [6]. Further optimization of location and size of ion beam synthesized NCs for memory application requires a deeper understanding of the mechanisms involved, which determine (i) the built-up of Si supersaturation by high-fluence ion implantation and (ii) NC formation by phase separation. For that aim, process simulations were divided into two steps. The Si implantation was studied using the binary collision code TRIDYN [7], which includes dynamic target changes. The phase separation of Si from SiO 2 during subsequent annealing has been simulated with a kinetic lattice Monte-Carlo code, which describes the thermally activated processes.The TRIDYN depth profiles are shown in Fig. 1 for 1 keV Si + ion implantation into SiO 2 . TRIDYN takes into account dynamic target changes due to ion deposition, ion erosion and ion beam mixing. The input parameters required by the simulation include the displacement and surface binding energies of target atoms. The displacement energies E d for both, Si and O, were assumed to be 8 eV. This value proved to yield satisfactory agreement between earlier TRIDYN simulations of ion mixing and experiments [8] and is also consistent with the choice of Sigmund and Gras-Marti [9] in their theoretical treatment of ion m...

show abstract

mentioning

confidence: 99%

mentioning

confidence: 99%

Size and location control of Si nanocrystals at ion beam synthesis in thin SiO2 films

Mueller

Heinig

Moeller

2002

Applied Physics Letters

View full text Add to dashboard Cite

show abstract

“…A novel memory structure using electrically isolated charge-storage nodes as a floating gate has been proposed, as shown in Figure 15.2b and c. The leakage path may fail the corresponding memory node only, hence the reliability and the retention time can be improved remarkably. On the other hand, a much thinner tunneling oxide film switches tunnel currents from the conventional Fowler-Nordheim (FN) tunneling to direct tunneling in programming and erasing processes, hence allowing a faster operation speed and a satisfied endurance [16]. The electrically isolated charge storage nodes, currently employed, rely on the localized defects in silicon nitride films [17] or the confinement in semiconductor quantum dots (QDs) [18].…”

Section: Emerging Nc-si Flash Memory Devicesmentioning

confidence: 99%

Silicon Nanocrystal Flash Memory

Oda

Huang

2010

Silicon Nanocrystals

View full text Add to dashboard Cite

“…De Salvo et al [19] suggest technology which could be used with nanowires to provide nanoscale floating-gate devices. Alternately, Huang et al describe a selective oxide growth scheme which has been used to provide one-time-programmable field-effect junctions [9].…”

Section: A Devicementioning

confidence: 99%

Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches

DeHon

2005

IEEE Trans. Nanotechnology

View full text Add to dashboard Cite

Abstract-Multiple techniques have now been proposed using random addressing to build demultiplexers which interface between the large pitch of lithographically patterned features and the smaller pitch of self-assembled sublithographic nanowires. At the same time, the relatively high defect rates expected for molecular-sized devices and wires dictate that we design architectures with spare components so we can map around defective elements. To accommodate and mask both of these effects, we introduce a programmable addressing scheme which can be used to provide deterministic addresses for decoders built with random nanoscale addressing and potentially defective wires. We describe how this programmable addressing scheme can be implemented with emerging, nanoscale building blocks and show how to build deterministically addressable memory banks. We characterize the area required for this programmable addressing scheme. For 2048 2048 memory banks, the area overhead for address correction is less than 33%, delivering net memory densities around 10 11 b/cm 2 .

show abstract

Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices

Cited by 142 publications

References 48 publications

Size and location control of Si nanocrystals at ion beam synthesis in thin SiO2 films

Size and location control of Si nanocrystals at ion beam synthesis in thin SiO2 films

Silicon Nanocrystal Flash Memory

Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches

Contact Info

Product

Resources

About