Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches

Abstract

Abstract-Multiple techniques have now been proposed using random addressing to build demultiplexers which interface between the large pitch of lithographically patterned features and the smaller pitch of self-assembled sublithographic nanowires. At the same time, the relatively high defect rates expected for molecular-sized devices and wires dictate that we design architectures with spare components so we can map around defective elements. To accommodate and mask both of these effects, we introduce a programmable addressing scheme which can be used to provide deterministic addresses for decoders built with random nanoscale addressing and potentially defective wires. We describe how this programmable addressing scheme can be implemented with emerging, nanoscale building blocks and show how to build deterministically addressable memory banks. We characterize the area required for this programmable addressing scheme. For 2048 2048 memory banks, the area overhead for address correction is less than 33%, delivering net memory densities around 10 11 b/cm 2 .

Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits

“…This hybrid resistor/FET-logic demux has the same function as the pure FET-based demux solutions proposed in [13][14][15]. Due to the regularity of the pFETs array, it is reasonable to expect that the fabrication of pFET can be relatively easy.…”

“…Several possible solutions have been proposed to tackle this challenge, which may be categorized based on whether the microwire-to-nanowire accessibility is realized through direct mircowire-nanowire ohmic contact [9,11] or a logic circuit called microwire-to-nanowire demultiplexer (demux) [12][13][14][15][16]. All the proposed demux design solutions have a crossbar structure consisting of one layer of parallel nanowires and one layer of parallel microwires.…”

“…In prior work on demux design, the demultiplexing function is realized by implementing a single type of devices such as resistor [16], diode [12], or field effect transistor (FET) [13][14][15] at a subset of the microwire-nanowire crosspoints. Because the nonlinear nature of diode's and FET's electrical characteristics can well match the nonlinear nature of the desired demultiplexing function, diode-logic and FET-logic demuxes can, in principle, very well approximate the ideal demultiplexing behavior.…”

Stochastic nanoscale addressing for logic

“…This post-assembly configuration is accomplished by using a memory decoder to program the WIRED-OR portion of the nanoscale circuit (see Figure 2) [12]. Arguably, one might consider decoding technologies by which the logic decoder itself could be constructed via similar post-assembly configuration [14]. In this scenario, stochastically assembled memory decoders would be constructed to individually address N A input NWs, then write operations would permanently couple each of the NWs to a different MW.…”

Nanowire Addressing in the Face of Uncertainty

“…Although some proposals allow portions of a NW's codewords may be assigned deterministically [9], a stochastic decoder is still needed.…”