Experimental and Theoretical Analyses of the Electrical SOA of Rugged p-Channel LDMOS

Podgaynaya, Alevtina; Rudolf, Ralf; Pogány, D.; Gornik, E.; Stecher, M.

doi:10.1109/led.2010.2081337

Cited by 7 publications

(5 citation statements)

References 13 publications

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“…6(b) shows the dependence of the BV on T w as a function of N d . According to (1), higher N d entails larger T w to achieve the maximum BV. However, the BV descends sharply when T w is too large or too small, as a result of the premature breakdown caused by the potential lines concentration at the drain or source side.…”

Section: Resultsmentioning

confidence: 99%

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Ultralow ON-Resistance High-Voltage p-Channel LDMOS With an Accumulation-Effect Extended Gate

Luo

Tan

Wei

et al. 2016

IEEE Trans. Electron Devices

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The high ON-resistance and the limited breakdown voltage (BV) are the two major issues for the p-channel lateral double-diffused MOSFET (pLDMOS). To solve the two issues, an ultralow specific ON-resistance (R ON,sp ) pLDMOS with improved BV is proposed and investigated by simulation. It features an extended gate (EG) with accumulation effect over the drift region and a P + floating layer (PFL) in the N-sub. In the ON-state, the EG induces the hole accumulation layer along the drift region surface, providing an ultralow-resistance conducting path. This accumulation-type current transport mode makes R ON,sp almost independent of the drift region doping concentration (N d ) and contributes to a much lower R ON,sp , which greatly breaks through the silicon limit of R ON,sp ∝ BV 2.5 . In the OFF-state, the EG not only modulates the surface electric field (E-field) distribution to enhance the BV, but also helps deplete the drift region to increase the optimized N d , and thus further reduce R ON,sp . Moreover, the PFL is not depleted, and thus equipotential in the lateral direction. Therefore, the PFL not only modulates the bulk E-field distribution at the source and drain sides but also introduces an additional vertical diode to sustain a higher BV. Owing to the effects mentioned above, the simulated results show that the EG PFL pLDMOS decreases R ON,sp by 68% and increases the BV by 47% compared with the conventional pLDMOS.Index Terms-Breakdown voltage (BV), extended gate (EG) with accumulation effect, P + floating layer (PFL), R ON,sp , tradeoff.

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Section: Resultsmentioning

confidence: 99%

“…n-channel LDMOS (nLDMOS), owing to its advantages such as dispensability of a charge pump for gate driving [1], [2]. However, the specific ON-resistance (R ON,sp ) of the pLDMOS is much higher than that of the nLDMOS, because the mobility of holes is much lower than that of the electrons.…”

mentioning

confidence: 99%

Ultralow ON-Resistance High-Voltage p-Channel LDMOS With an Accumulation-Effect Extended Gate

Luo

Tan

Wei

et al. 2016

IEEE Trans. Electron Devices

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“…In high‐side switch applications, the p‐channel lateral double‐diffused metal–oxide–semiconductor field‐effect transistor (pLDMOS) has more advantages than the n‐channel LDMOS (nLDMOS) such as dispensability of a charge pump for gate driving [1, 2]. However, the mobility of electrons is pretty much higher than that of the holes, which results that the specific on‐resistance ( R on,sp ) of the pLDMOS is much higher than that of the nLDMOS [3].…”

Section: Introductionmentioning

confidence: 99%

PSOI pLDMOS with n‐buried layer

Yue

Yang

et al. 2017

Micro & Nano Letters

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Partial-silicon (Si)-on-insulator p-channel lateral double-diffused metal-oxide-semiconductor field-effect transistor with n-buried layer (NBL PSOI pLDMOS) is proposed. One feature of the device is an Si window under the drain offers a heat conduction path to alleviate the selfheating effect. Meanwhile, a fully depleted NBL on the bottom surface of the Si layer provides a large amount of ionised donors to enhance the electric field of the buried oxide (BOX) layer. The NBL can prevent the substrate leakage phenomenon of the PSOI pLDMOS. There is a triple reduced surface field structure in the p-drift region. Some equipotential lines spread into the p-substrate through the Si window. Furthermore, the assistant depletion caused by the NBL increases the p-drift region concentration, which achieves a lower specific on-resistance (R on,sp). With 20 µm p-drift region length and 1 µm BOX thickness, the NBL PSOI pLDMOS obtains a higher breakdown voltage (BV) of 289 V, which is increased by 88.9 and 43.8% compared with the Con SOI and NBL SOI pLDMOS, respectively. The R on,sp is decreased by 82.3 and 17.2%, respectively. The figure of merit (FOM = BV 2 /R on,sp) is 1.65 MW cm −2. A lower maximum surface temperature of 312.3 K is obtained.

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“…Technology computer aided design (TCAD) simulations are performed results of electric field and impact ionization (I-I) rate are analyzed to explain the experimental data. Finally, electrical safe-operating-area (E-SOA) [21][22][23][24][25][26][27][28][29] of devices is investigated. The device with gradual junction profile also has wider E-SOA range.…”

Section: Introductionmentioning

confidence: 99%

Characteristics of Lateral Diffused Metal–Oxide–Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide

Yan

Chen

Lin

et al. 2013

Jpn. J. Appl. Phys.

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Characteristics of lateral diffused metal–oxide–semiconductor (LDMOS) transistors with gradual junction profile by self-alignment implant through dual thicknesses of screen oxide are presented in this letter. Compared with LDMOS transistors with traditional junction profile, this new device shows improved off-state breakdown voltage, less severe in Kirk effect, and wider electrical safe operating area; without sacrificing device drivability. Technology computer aided design (TCAD) simulation results reveal that this new device has smaller electric field both in off- and on-state bias conditions. Hot-carrier induced degradation of this new device under various stress conditions is also investigated and compared with that of the device with traditional junction profile.

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Experimental and Theoretical Analyses of the Electrical SOA of Rugged p-Channel LDMOS

Cited by 7 publications

References 13 publications

Ultralow ON-Resistance High-Voltage p-Channel LDMOS With an Accumulation-Effect Extended Gate

Ultralow ON-Resistance High-Voltage p-Channel LDMOS With an Accumulation-Effect Extended Gate

PSOI pLDMOS with n‐buried layer

Characteristics of Lateral Diffused Metal–Oxide–Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide

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