Execution-driven tools for parallel simulation of parallel architectures and applications

Poulsen, David K.; Yew, Pen-Chung

doi:10.1145/169627.169852

Cited by 21 publications

(9 citation statements)

References 19 publications

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“…Experimental results are acquired through execution-driven simulations of parallel application codes using EPG-sim [10]. Simulations are driven by parallel versions of Perfect Benchmarks (R) codes [11].…”

Section: Experimental Frameworkmentioning

confidence: 99%

Data Prefetching and Data Forwarding in Shared Memory Multiprocessors

Poulsen

Yew

1994

1994 International Conference on Parallel Processing (ICPP'94)

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This paper studies and compares the use of data prefetching and an alternative mechanism, data forwarding, for reducing memory latency due to interprocessor communication in cache coherent, shared memory multiprocessors. Two multiprocessor prefetching algorithms are presented and compared. A simple blocked vector prefetching algorithm, considerably less complex than existing software pipelined prefetching algorithms, is shown to be effective in reducing memory latency and increasing performance. A Forwarding Write operation is used to evaluate the effectiveness of forwarding. The use of data forwarding results in significant performance improvements over data prefetching for codes exhibiting less spatial locality. Algorithms for data prefetching and data forwarding are implemented in a parallelizing compiler. Evaluation of the proposed schemes and algorithms is accomplished via execution-driven simulation of large, optimized, parallel numerical application codes with loop-level and vector parallelism. More data, discussion, and experiment details can be found in [1].

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Section: Experimental Frameworkmentioning

confidence: 99%

Data Prefetching and Data Forwarding in Shared Memory Multiprocessors

Poulsen

Yew

1994

1994 International Conference on Parallel Processing (ICPP'94)

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“…After the compiler marking, we instrument the benchmarks to generate events that reflect the behavior of the codes executing on different target architectures. Execution-driven simulations [29] are used to verify the compiler algorithm and to evaluate the performance of compiler-directed coherence schemes. Fig.…”

Section: Experimentationmentioning

confidence: 99%

Compiler analysis for cache coherence: interprocedural array data-flow analysis and its impact on cache performance

Choi

Yew

2000

IEEE Trans. Parallel Distrib. Syst.

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AbstractÐIn this paper, we present compiler algorithms for detecting references to stale data in shared-memory multiprocessors. The algorithm consists of two key analysis techniques, stale reference detection and locality preserving analysis. While the stale reference detection finds the memory reference patterns that may violate cache coherence, the locality preserving analysis minimizes the number of such stale references by analyzing both temporal and spatial reuses. By computing the regions referenced by arrays inside loops, we extend the previous scalar algorithms [9] for more precise analysis. We develop a full interprocedural array data-flow algorithm, which performs both bottom-up side-effect analysis and top-down context analysis on the procedure call graph to further exploit locality across procedure boundaries. The interprocedural algorithm eliminates cache invalidations at procedure boundaries, which were assumed in the previous compiler algorithms [9]. We have fully implemented the algorithm in the Polaris parallelizing compiler [28]. Using execution-driven simulations on Perfect Club benchmarks, we demonstrate how unnecessary cache misses can be eliminated by the automatic stale reference detection. The algorithm can be used to implement cache coherence in the sharedmemory multiprocessors that do not have hardware directories, such as Cray T3D [21].

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“…Experimental results are acquired through execution-driven simulations of large, optimized, parallel numerical benchmarks by using EPG-sim [9], a system of execution-driven tools for studying parallel architectures, compiler algorithms, and applications. Simulations model a shared memory architecture with directory-based cache coherence and are driven by parallel versions of Perfect Benchmarks [10] codes that have been optimized for the modeled architecture.…”

Section: Introductionmentioning

confidence: 99%