Data Prefetching and Data Forwarding in Shared Memory Multiprocessors

Poulsen, David K.; Yew, Pen-Chung

doi:10.1109/icpp.1994.81

Cited by 44 publications

(32 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Rangan et al in [23], study alternatives to hardware support for pipelined streaming. They conclude that optimizations for write-forwarding [16,22,2,15] at line boundaries, synchronization counters in L2 caches (which they do not describe) and dedicated receive-side caches in a separate address space for pipelined streaming data, can reach the performance of heavyweight hardware support. Our design integrates equivalent mechanisms inside caches augmented with RDMA for efficient bulk transfers.…”

Section: Related Work and Contributionsmentioning

confidence: 99%

On-chip communication and synchronization mechanisms with cache-integrated network interfaces

Kavadias

Katevenis

Zampetakis

et al. 2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

View full text Add to dashboard Cite

Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces (NIs), appropriate for scalable multicores, that combine the best of two worlds -the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized NI functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a mechanism for software configurable synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, memory barriers for explicitly-selected accesses of arbitrary size, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and evaluated the on-chip communication performance on the prototype as well as on a CMP simulator with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.

show abstract

Section: Related Work and Contributionsmentioning

confidence: 99%

On-chip communication and synchronization mechanisms with cache-integrated network interfaces

Kavadias

Katevenis

Zampetakis

et al. 2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

View full text Add to dashboard Cite

show abstract

“…Similar data forwarding mechanisms have been proposed in the literature: the forwarding write, (36) and the DASH deliver. (21) DASH also had a producer-prefetch mechanism for pushing data to a set of consumers in shared state.…”

Section: Related Workmentioning

confidence: 96%

Inferential Queueing and Speculative Push

Rajwar

Kägi

Goodman

2004

International Journal of Parallel Programming

View full text Add to dashboard Cite

Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of two mechanisms to reduce these communication latencies: Inferentially Queued locks (IQLs) and Speculative Push (SP). With IQLs, the processor infers the existence, and limits, of a critical section from the use of synchronization instructions and joins a queue of lock requestors, reducing synchronization delay. The SP mechanism extracts information about program structure by observing IQLs. SP allows the cache controller, responding to a request for a cache line that likely includes a lock variable, to predict the data sets the requestor will modify within the associated critical section. The controller then pushes these lines from its own cache to the target cache, as well as writing them to memory. Overlapping the protected data transfer with that of the lock can substantially reduce the communication latencies within critical sections. By pushing data in exclusive state, the mechanism can collapse a read-modify-write sequences within a critical section into a single local cache access. The write-back to memory allows the receiving cache to ignore the push. Neither mechanism requires any programmer or compiler support nor any instruction set changes. Our experiments demonstrate that IQLs and SP can improve performance of applications employing frequent synchronization.

show abstract

“…In order to extend this system to an arbitrary network some form of consumer prediction [5] would be needed 1 . Methods similar to this are used in software [6] to identify likely consumers using profiling and other compiler techniques, and insert special instructions to forward data to them at appropriate times. Consumer set prediction [5], [7] attempts to identify the processors which will consume data.…”

Section: Introductionmentioning

confidence: 99%

Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors

Leventhal

Franklin

2006

2006 International Conference on Computer Design

View full text Add to dashboard Cite

Abstract-Recent research has shown that forwarding speculative data to other processors before it is requested can improve the performance of multiprocessor systems. The most recent work in speculative data forwarding places all of the processors on a single bus, allowing the data to be forwarded to all of the processors at the same cost as any subset of the processors. Modern multiprocessors however often employ more complex switching networks in which broadcast is expensive. Accurately predicting the consumers of data can be challenging, especially in the case of programs with many shared data structures.Past consumer predictors rely on simple prediction mechanisms, a single table lookup followed by a static mapping of the table values onto a prediction. We make two main contributions in this paper. First, we show how to reduce the design space of consumer predictors to a set of interesting predictors, and how previous consumer predictors can be tuned to expand the range of available performance. Second, we propose a perceptron consumer predictor that dynamically adapts its reaction to the system behavior, and uses more history information than previous consumer predictors. This predictor outperforms the previous predictors by 21% while using only 1KByte more storage than previous predictors.

show abstract

Data Prefetching and Data Forwarding in Shared Memory Multiprocessors

Cited by 44 publications

References 12 publications

On-chip communication and synchronization mechanisms with cache-integrated network interfaces

On-chip communication and synchronization mechanisms with cache-integrated network interfaces

Inferential Queueing and Speculative Push

Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors

Contact Info

Product

Resources

About