Compiler analysis for cache coherence: interprocedural array data-flow analysis and its impact on cache performance

Abstract

AbstractÐIn this paper, we present compiler algorithms for detecting references to stale data in shared-memory multiprocessors. The algorithm consists of two key analysis techniques, stale reference detection and locality preserving analysis. While the stale reference detection finds the memory reference patterns that may violate cache coherence, the locality preserving analysis minimizes the number of such stale references by analyzing both temporal and spatial reuses. By computing the regions referenced by arrays inside loops, we extend the previous scalar algorithms [9] for more precise analysis. We develop a full interprocedural array data-flow algorithm, which performs both bottom-up side-effect analysis and top-down context analysis on the procedure call graph to further exploit locality across procedure boundaries. The interprocedural algorithm eliminates cache invalidations at procedure boundaries, which were assumed in the previous compiler algorithms [9]. We have fully implemented the algorithm in the Polaris parallelizing compiler [28]. Using execution-driven simulations on Perfect Club benchmarks, we demonstrate how unnecessary cache misses can be eliminated by the automatic stale reference detection. The algorithm can be used to implement cache coherence in the sharedmemory multiprocessors that do not have hardware directories, such as Cray T3D [21].

Hardware and compiler-directed cache coherence in large-scale multiprocessors: Design considerations and performance study

“…Time-reads with o sets 2 and 3 are generated for the last two read references to variables W and X, assuming they are modi ed 2 and 3 epochs before the procedure Q returns. The details of compiler algorithms are beyond the scope of this paper and are described in 15,16].…”

“…We then transform the program in the GSA form back to the original program with the reference marking information, and generate appropriate cache and memory operations. The guarded execution technique can be used to further optimize code generation 15,16].…”

Exact Distributed Invalidation

“…Early work invalidated all cached data at each parallel region or epoch. More recent schemes have used tags or timestamps to maintain cached data across epochs [2,3,5]. Some schemes use a compiler controlled directory to help in runtime dependence analysis, whilst others remove the need for a directory altogether [2,11,6,12,15,17].…”

“…In [7], vectorisation is used to minimise the overhead of redundant invalidation when using RDS analysis. Array data-flow analysis was used in [5] to detect and eliminate stale data references. However, the greater accuracy of this method was not exploited in determining the coherence action of the entire program.…”

Tuning data replication for improving behavior of MPSoC applications

“…Lim and Yew [6] propose a strategy that enforces cache coherence by prefetching the up-to-date data corresponding potentially stale references from the main memory. Choi and Yew [3] study compiler support for cache coherence in large-scale multiprocessor machines. In contrast to these studies, our target architecture is a bus-based MPSoC, and our main goal is optimizing energy consumption.…”