Evolutionary functional recovery in virtual reconfigurable circuits

Abstract

A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device developed using an ordinary FPGA in order to easily implement evolvable hardware applications. While a fast partial runtime reconfiguration and application-specific programmable elements represent the main advantages of VRC, the main disadvantage of the VRC is the area consumed. This study describes experiments conducted to estimate how the use of VRC influences the dependability of FPGAbased evolvable systems. It is shown that these systems are not as sensitive to faults as their area-demanding implementations might suggest. An evolutionary algorithm is utilized to design fault tolerant circuits as well as to perform an automatic functional recovery when faults are detected in the configuration memory of the FPGA. All the experiments are performed on models of reconfigurable devices.

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

“…Typical performance plots in terms of fitness with respect to time for both NDER and CER are illustrated in Figure 10. This overall behavior of conventional GA may be attributed to the I/O characteristics and the sizes of the chosen circuits, as compared to the ones used in previous works [12], [14], [23], [27], [39], [40]. For instance, it is shown in [40] that the recovery time increases with increasing number of output lines.…”

Intrinsic evolvable hardware platform for digital circuit design and repair using genetic algorithms

“…A promising technique called the Virtual Reconfigurable Circuit (VRC) method was proposed by Sekanina in [7] and [8] and also in a similar work by Glette and Torresen [9]. This method does not change the bitstream of the FPGA itself, but rather changes the register values of a reconfigurable circuit already implemented on the FPGA, and obtains virtual reconfigurability.…”

Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems

“…Test case is a 3×2-bit multiplier using a simulator at CLB/LUT level. In [14], a 1-bit full adder and a 2-bit multiplier are used as test circuits for the VRC case at logic function level, considering faults only in the configuration memory. Again, a heuristically seeded EA exhibits more stable behavior than a randomly seeded one.…”