Evolutionary design of combinational logic circuits using VRA processor

Abstract

This paper presents a virtual reconfigurable architecture (VRA)-based evolvable hardware for automatic synthesis of combinational logic circuits. The VRA processor is implemented on a Xilinx FPGA and works through two-stage evolutions: (1) finding a functional circuit, and (2) minimizing the number of gates used. To optimize the algorithm performance in the evolutionary process, a self-adaptive mutation rate control scheme is introduced. The efficiency of the proposed methodology is tested with the evolution of a 3-bit multiplier. The obtained results demonstrate that our approach improves the evolutionary design of electronic circuits in terms of quality of the evolved circuit as well as the computational effort. Keywords: evolvable hardware, self-adaptive mutation rate control, two-stage evolution, VRA Classification: Integrated circuits References[1] S. M. Cheang, K. H. Lee, and K. S. Leung, "Applying genetic parallel programming to synthesize combinational logic circuits," IEEE Trans. Evol. Comput., vol. 11, no. 4, pp. 503-520, Aug. 2007. [2] L. Sekanina and S. Friedl, "An evolvable combinational unit for FPGAs,"J. Computing and Informatics, vol. 23, no. 5, pp. 461-486, 2004.

A LUT manipulation based intrinsic evolvable system

“…7. The optimal 3-bit multiplier evolved by us has a comparative performance comparing with its competitors [6]. The performance comparisons are summarized in Table II.…”

“…7. An optimal evolved 3-bit multiplier (27 gates, 6 propagation gate delays) IEICE Electronics Express, Vol.11, No.4, 1-7 utilization saving over the VRC. In view of the varieties of EAs and benchmarks employed in the existing methods, configuration time cost is chosen as the criteria for evolution speed.…”

“…(1), m and n represent the number of bits of outputs and inputs of a circuit, respectively; w ij is the jth bit of the output for the ith input pattern; v ij is the desired output bit defined by truth table [6]. Fig.…”

“…Furthermore, the most important of these processing steps, place and route (PAR), is very slow and not deterministic, making it difficult to reliably generate slightly altered bitstream and observe incremental changes in order to infer the function of the altered locations [5]. A well-known alternative is using virtual reconfigurable circuits (VRC) [6], a reconfigurable layer built on top of the reconfigurable fabric that reduces the complexity of the reconfiguration process, creating a kind of application specific programmable elements. Drawbacks of VRCs are complained about area and delay overheads, as well as high power consumption.…”