Evolution of T-shaped gate lithography for compound semiconductors field-effect transistors

Abstract

T-shaped gate formation is a major processing step in the fabrication of high-performance field-effect transistor FET-based III-V devices. Traditional bilayer or trilayer E-beam lithography methods using PMMA/(PMMA&PMAA) copolymers are high-cost options which also lack the required critical dimension control for manufacturing. Lithography methods that use only a single layer of PMMA for the formation of T-shaped gate stem, and routine I-line resist lithography for the tee-top, i.e., hybrid T-shaped gates, have been developed and extensively used in manufacturing. This approach has also been extended to the fabrication of deep submicron T-shaped gates using all I-line optical lithography. Both chemical shrinks and chromeless phase-shift resolution enhancement techniques have been investigated.Index Terms-Field-effect transistor, GaAs, T-shaped gate.

Investigations of AlGaN/GaN HFETs utilizing post-metallization etching by nitric acid treatment

“…Moreover, it is known that the dimension of gate electrode plays an important role to affect the device performances of HFETs [8][9][10], such as the transconductance gain, current drive and high frequency characteristics. So far, lithography methods [11][12][13][14][15] have been proposed to reduce the feature size [16][17]. Ni/Au alloys were commonly used as a gate electrode of AlGaN/GaN HFETs [18][19][20].…”

Reduction of skin effect losses in double-level-T-gate structure

“…During the last three decades, the fabrication and performance of transistors operating in the GHz frequency range have been showing a rapid progress by introducing new material systems (e.g., GaAs/InGaAs 1-4 or AlGaN/GaN heterostructures [5][6][7] ), novel technological processes, [6][7][8][9] or new device geometries with decreasing gate dimensions. [10][11][12] The transistor scaling process has the drawback that the parasitic gate resistance increases linearly with decreasing gate length L g . A small gate length is crucial for the transistor speed; however, the increase of the gate resistance degrades the external device properties, especially the power gain.…”