Evidence of negative bias temperature instability in 4H-SiC metal oxide semiconductor capacitors

Marinella, Matthew; Schroder, D.K.; Isaacs-Smith, T.; Ahyi, A. C.; Williams, John R.; Chung, Gil Yong; Wan, Jian Wei; Loboda, Mark J.

doi:10.1063/1.2748327

Cited by 42 publications

(16 citation statements)

References 16 publications

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“…Under reverse gate bias stress, positive charge can be trapped at interface-states in near-interface defects, which are border traps [27]. These trapped charges play a role on the negative threshold voltage (V TH ) shift and also degrade channel carrier mobility [28,29]. A similar observation was reported in SiC MOSFETs, where a partially recoverable decrease in lifetime and increase in interface state density took place after reverse gate bias stress [30].…”

Section: Introductionsupporting

confidence: 58%

“…These observations suggest that the generation of field-induced surface traps at the ungated access region between gate and drain sides and electron detrapping effects from preexisting oxide traps induces the I DS, Max and R DS-ON degradation [38][39][40], turn-on and rise-time delay, and negative V TH shift [29,30], which is shown in Figures 5-7. The generation of ungated surface-state traps between the gate and source/drain contacts act as "virtual gates", modulating the underlying depletion region through changes in the density of negatively charged traps.…”

Section: Pulsed Negative Gate Bias Stress (Gate Lag)mentioning

confidence: 82%

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Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications

2020

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We present a detailed study of dynamic switching instability and static reliability of a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High-Electron-Mobility-Transistor (MIS-HEMT) based cascode switch under off-state (negative bias) Gate bias stress (VGS, OFF). We have investigated drain channel current (IDS, Max) collapse/degradation and turn-on and rise-time (tR) delay, on-state resistance (RDS-ON) and maximum transconductance (Gm, max) degradation and threshold voltage (VTH) shift for pulsed and prolonged off-state gate bias stress VGS, OFF. We have found that as stress voltage magnitude and stress duration increases, similarly IDS, Max and RDS-ON degradation, VTH shift and turn-on/rise time (tR) delay, and Gm, max degradation increases. In a pulsed off-state VGS, OFF stress experiment, the device instabilities and degradation with electron trapping effects are studied through two regimes of stress voltages. Under low stress, VTH shift, IDS collapse, RDS-ON degradation has very minimal changes, which is a result of a recoverable surface state trapping effect. For high-stress voltages, there is an increased and permanent VTH shift and high IDS, Max and RDS-ON degradation in pulsed VGS, Stress and increased rise-time and turn-on delay. In addition to this, a positive VTH shift and Gm, max degradation were observed in prolonged stress experiments for selected high-stress voltages, which is consistent with interface state generation. These findings provide a path to understand the failure mechanisms under room temperature and also to accelerate the developments of emerging GaN cascode technologies.

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Section: Introductionsupporting

confidence: 58%

Section: Pulsed Negative Gate Bias Stress (Gate Lag)mentioning

confidence: 82%

Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications

2020

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“…8,9) Although many studies on positive gate bias stress have been reported, [7][8][9][10][11][12][13][14][15][16][17][18] there are only a few studies on negative gate bias stress. [19][20][21][22][23] In addition to detrapping phenomena, negative bias temperature stress instability is possibly underestimated by the conventional I d -V g method because the holes trapped by negative stress are recombined with channel electrons owing to the positive V g bias during I d -V g measurement. To suppress the effect of recombination, a method of evaluating hole trapping through capacitance-voltage (C-V ) measurement had been reported.…”

Section: Introductionmentioning

confidence: 99%

Hole trapping in SiC-MOS devices evaluated by fast-capacitance–voltage method

Hayashi

Sometani

Hatakeyama

et al. 2018

Jpn. J. Appl. Phys.

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We demonstrated a fast-capacitance-voltage (CV) method for the evaluation of the number and location of holes trapped in a 4H-SiC MOS device under negative gate bias stress. The number of trapped holes was carefully estimated by suppressing recombination and detrapping during stress relaxation. It was found that a large number of holes trapped in a short stress time were reduced by nitridation, and that the hole trapping in a longstress-time region was accelerated by increases in temperature and electric field for a stress. From the results, we determined the respective model for hole trapping and detrapping.

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“…After the stress, the same transition takes place over approximately = -1 V to = +5 V, giving a total of 6 V, or an increase of 4 V! This large stretch out of the C-V curve is often associated with an increased density of interface states ( ) [14], such as when NBTI [15] is induced (however, since in this case is positive, this is not NBTI). In this case, it appears that an increase of interface states was caused by the injection of electrons into the SiC/SiO 2 interface.…”

Section: Bias-temperature-stress Measurements On N-body Mos Capacitorsmentioning

confidence: 99%

“…BTS measurements have also been used to uncover and study a number of non-idealities in the SiC-SiO 2 MOS capacitor such as negative bias temperature instability (NBTI) [15], charge injection [15,16], and mobile ions [17]. The careful study and optimization of these effects is necessary to create a robust SiC-SiO 2 interface suitable for a SiC MOSFET.…”

Section: Bias-temperature-stress Measurements On N-body Mos Capacitorsmentioning

confidence: 99%

Stress testing on silicon carbide electronic devices for prognostics and health management.

Kaplar¹,

Brock²,

Marinella³

et al. 2011

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Power conversion systems for energy storage and other distributed energy resource applications are among the drivers of the important role that power electronics plays in providing reliable electricity. Wide band gap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) will help increase the performance and efficiency of power electronic equipment while condition monitoring (CM) and prognostics and health management (PHM) will increase the operational availability of the equipment and thereby make it more cost effective. Voltage and/or temperature stress testing were performed on a number of SiC devices in order to accelerate failure modes and to identify measureable shifts in electrical characteristics which may provide early indication of those failures. Those shifts can be interpreted and modeled to provide prognostic signatures for use in CM and/or PHM. Such experiments will also lead to a deeper understanding of basic device physics and the degradation mechanisms behind failure. 4 ACKNOWLEDGMENTS

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Evidence of negative bias temperature instability in 4H-SiC metal oxide semiconductor capacitors

Cited by 42 publications

References 16 publications

Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications

Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications

Hole trapping in SiC-MOS devices evaluated by fast-capacitance–voltage method

Stress testing on silicon carbide electronic devices for prognostics and health management.

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