Evidence of InterDiffusion Effect In Stacked Polycrystalline Sige/Si Layers For Cmos Gate Application

Abstract

Poly-SiGe stacked gates with Ge content ([Ge])varying between zero and 100% have been fabricated using an industriel single-wafer machine. These poly-SiGe layers were characterised and fully integrated in a 0.18 pm CMOS process. Interdiffusion of Si and Ge upon subsequent annealing of the structure has been observed and studied. This interdiffusion effect was found to be responsible for the discrepancy observed between theoretical and practical values of the Ge workfunction ɸms evaluated from our electrical measurements and from those of different authors. A technique for the limitation of this interdiffusion effect has then been developped and is described.

Reduced pressure chemical vapor deposition of Ge thick layers on Si(001), Si(011) and Si(111)

“…One, which has been proposed initially by Colace et al in 1998 [9], followed quite closely by Hernandez et al [10], relies on the deposition of a low-temperature Ge ''seed'' layer, followed by the deposition of a high-temperature Ge layer [2,[9][10][11][12][13][14][15]. The low temperature (LT:330 1C-450 1C) adopted for the first Ge layer plastically relaxes the strain in the Ge film without the nucleation of any 3D islands.…”

Reduced pressure-chemical vapor deposition of intrinsic and doped Ge layers on Si(001) for microelectronics and optoelectronics purposes

“…Please note for sample (a) the presence of bi-atomic steps (as in Ref. [14]). We have plotted in Fig.…”

“…One, which has been proposed initially by Colace et al in 1998 [3], followed quite closely by Hernandez et al [14], relies on the deposition of a low-temperature Ge layer, followed by the deposition of a high-temperature Ge layer. The low-temperature (330-450 1C [5], [14][15][16][17][18][19]) adopted for the first Ge layer plastically relaxes the strain in the Ge film without the nucleation of any 3D islands.…”

“…The low-temperature (330-450 1C [5], [14][15][16][17][18][19]) adopted for the first Ge layer plastically relaxes the strain in the Ge film without the nucleation of any 3D islands. The high temperature (600-850 1C [5], [14][15][16][17]) used for the growth of the second, topmost, Ge layer lowers the dislocation density and reduces the overall deposition time.…”

Impact of the H2 anneal on the structural and optical properties of thin and thick Ge layers on Si; Low temperature surface passivation of Ge by Si

“…Chemical mechanical polishing is then mandatory to recover smooth surfaces. Another route, initially proposed by Colace et al [17] (followed quite closely by Hernandez et al [18]), relies on the low-temperature growth of a thin Ge ''seed'' layer, followed by the high temperature deposition of a thick Ge layer [2,[17][18][19][20][21][22][23]. The Low Temperature (LT: 330-450 1C) adopted for the first Ge layer plastically relaxes the strain in the Ge film without any 3D islanding.…”