Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits

Ruiz, Gustavo A.

doi:10.1109/4.663566

Cited by 37 publications

(12 citation statements)

References 21 publications

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“…In table 1, data related to a group of self-timed adders realized using different architectures and full-custom design approaches are reported (Ruiz 1998, Ruiz andManzano 2000). To the best of our knowledge, they are the fastest self-timed adders accomplished with post-layout experiments.…”

Section: Post-layout Simulation Resultsmentioning

confidence: 97%

“…Binary addition is the most used digital operation, thus self-timed adders, especially, have recently aroused considerable interest (Cheng et al 1997, Johnson and Akella 1998, Ruiz 1998, Won and Choi 1999, Ruiz and Manzano 2000, Garside 1993, De Gloria and Olivieri 1996, Kinniment 1996, Escriba`and Carrasco 1996, Nowick 1996, Nowick et al 1997, Corsonello et al 1999a, 1999b, Cheng et al 2000. Laying out the circuits described in the above papers requires a full-custom approach to be used.…”

Section: Introductionmentioning

confidence: 99%

“…In fact, non-conventional data encoding and multiple output gates are often required. Typically, to realize efficient self-timed circuits (Cheng et al 1997, Johnson and Akella 1998, Ruiz 1998, Won and Choi 1999, and Cho Ruiz and Manzano 2000 dynamic CMOS logic and particular delay assumptions (e.g. bounded delays) are used (Furber and Liu 2000).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An efficient self-timed adder realized using conventional CMOS standard cells

Perri

Corsonello

Cocorullo

2003

International Journal of Electronics

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Usually, efficient self-timed adders are realized using the dynamic differential cascode voltage switch logic. This allows the end-completion to be easily detected, but it makes circuit design and testing very complex, compelling the production of full-custom layouts and leading to a very long time before marketing. This paper presents a new 56-bit high-speed self-timed adder realized with conventional AMS 0.35 mm CMOS standard cells. The proposed circuit uses overlapped execution circuits, which exploit the initialization time that always elapses between two consecutive addition operations. Compared to several self-timed adders existing in the literature, the addition circuit proposed here shows brilliant advantages in terms of speed-performance, silicon area occupancy and power dissipation.

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Section: Post-layout Simulation Resultsmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An efficient self-timed adder realized using conventional CMOS standard cells

Perri

Corsonello

Cocorullo

2003

International Journal of Electronics

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“…The dynamic power dissipation of 16-bit RCA is reduced by minimizing the internal node capacitances and achieved good delay performance 5 . The efficient implementation of RCA in differential logic is carried out and achieved best performance for random input operands 6 . The timing error mitigation is done in RCA and compared it with other adders 7 .…”

Section: Literature Review and Related Workmentioning

confidence: 99%

Analysis and Design of Subthreshold Leakage Power-aware Ripple Carry Adder at Circuit-level Using 90nm Technology

Amuthavalli

Gunasundari

2015

Procedia Computer Science

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The design space of Wireless Sensor Network mainly focuses on power-aware circuits. As the eventtriggering nature of the circuit places itself in Standby mode for longer time, the leakage power shoots up and increases its power consumption. Out of many leakage components, subthreshold leakage power (P sub_leak ) is the dominant one, which is reduced by the proposed technique called Short-Pulse Power Gated Approach (SPOGA). The adder is the basic digital subsystem in the signal processing blocks and Ripple Carry Adder (RCA) is analyzed in the context of P sub_leak at circuit-level of abstraction using Cadence GPDK090. The P sub_leak reduces significantly with the 35% to 40% leakage savings in comparison with conventional and Multi-Threshold CMOS (MTCMOS) based RCA.

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“…Two types of ALUs were designed and the difference in both the ALUs was of adder type. In the first one a ripple carry adder [8][9][10][11][12][13][14][15][16][17] was used while in the second one a pre-fix tree of sklansky type adder [18][19][20][21][22][23][24][25] was used. The adder is a very important component in digital systems, so lot of research has been done in past on various types of adders to improve the speed and area requirements [26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41].…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow

Buzdar¹,

Sun²,

Buzdar³

2016

ijacsa

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Abstract-An Arithmetic Logic Unit (ALU) is the heart of every central processing unit (CPU) which performs basic operations like addition, subtraction, multiplication, division and bitwise logic operations on binary numbers. This paper deals with implementation of a basic ALU unit using two different types of adder circuits, a ripple carry adder and a sklansky type adder. The ALU is designed using application specific integrated circuit (ASIC) platform where VHDL hardware description language and standard cells are used. The target process technology is 130nm CMOS from the foundry ST Microelectronics. The Cadence EDA tools are used for the ASIC implementation. A comparative analysis is provided for the two ALU circuits designed in terms of area, power and timing requirements.

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Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits

Cited by 37 publications

References 21 publications

An efficient self-timed adder realized using conventional CMOS standard cells

An efficient self-timed adder realized using conventional CMOS standard cells

Analysis and Design of Subthreshold Leakage Power-aware Ripple Carry Adder at Circuit-level Using 90nm Technology

Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow

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