Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs

Abstract-Implementation-level attacks are nowadays well known and most designers of security embedded systems are aware of them. However, both the number of vulnerabilities and of protections have seriously grown since the first public reporting of these threats in 1996. It is thus difficult to assess the correct countermeasures association to cover all the possible attack pathes. The goal of this paper is to give a clear picture of the possible adequation between actually risks and mitigation techniques. A specific focus is made on two protection techniques addressing primarily side-channel attacks: masking and hiding. For the first time, we provide with a way to estimate a tradeoff depending on the environmental conditions (amount of noise) and on the designer skills (ability to balance the design). This tradeoff is illustrated in a decision diagram, helpful for the security designer to justify choices and to account for the cost overhead.

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“…• (x t , x f ) = (0, 0) or (1, 1) in precharge phase, which prevents memory effects and enables positive (glitchfree [34]) computation, and…”

Section: B Hidingmentioning

confidence: 99%

Vade mecum on side-channels attacks and countermeasures for the designer and the evaluator

Guilley

Meynard

Nassar

et al. 2011

2011 6th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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“…Some previous articles [8,9] already described the mapping of dual-rail logics into FPGA. However, all of them target 4 → 1 look-up-table FPGAs.…”

Section: Place-and-routementioning

confidence: 99%

“…As WDDL is based on a standard cell flow, it is the most suited for FPGA implementation. Guidelines for synthesis can be found in [8,9]. We notice incidentally that those articles target 4 → 1 LuT-based FPGA technologies and thus do not take full advantage of the advanced features of modern FPGAs, such as ALM (Adaptative Logic Modules) configurable blocks and 2 International Journal of Reconfigurable Computing dual-output logic blocks.…”

Section: Introductionmentioning

confidence: 99%

Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics

Sauvage

Nassar

Guilley

et al. 2010

International Journal of Reconfigurable Computing

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FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally gave evidence that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, so far, this gain turned out to be lower for FPGAs than for ASICs. The solutions demonstrated in this article exploit the dual-output of modern FPGAs to achieve a better balance of dual-rail interconnections. However, we expect that an in-depth analysis of routing resources power consumption could still help reduce the interconnect differential leakage.

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“…To avoid glitches it is necessary that all the gates in the design should be positive in nature. To ensure this in WDDL, the design is synthesized with a library consisting of only positive gates (like AND, OR) [24]. As shown in figure 3, a WDDL AND gate consists of an AND gate (G) and a complementary OR gate (G * , satisfying A point worth noting in figure 3 is that one flip-flop in the single-rail design is replaced by four flip-flops in the WDDL design.…”

Section: Wave Dynamic Differential Logicmentioning

confidence: 99%

WDDL is Protected against Setup Time Violation Attacks

Selmane

Bhasin

Guilley

et al. 2009

2009 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)

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Abstract-In order to protect crypto-systems against side channel attacks various countermeasures have been implemented such as dual-rail logic or masking. Faults attacks are a powerful tool to break some implementations of robust cryptographic algorithms such as AES and DES. Various kind of fault attacks scenarios have been published. However, very few publications available in the public literature detail the practical realization of such attacks. In this paper we present the result of a practical fault attack on AES in WDDL and its comparison with its non-protected equivalent. The practical faults on an FPGA running an AES encryptor are realized by under-powering it and further exploited using Piret's attack. The results show that WDDL is protected against setup violation attacks by construction because a faulty bit is replaced by a null bit in the ciphertext. Therefore, the fault leaks no exploitable information. We also give a theoretical model for the above results. Other references have already studied the potential of fault protection of the resynchronizing gates (delayinsensitive). In this paper, we show that non-resynchronizing gates (hence combinatorial DPL such as WDDL) are natively immune to setup time violation attacks.

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Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs

Cited by 20 publications

References 19 publications

Vade mecum on side-channels attacks and countermeasures for the designer and the evaluator

Vade mecum on side-channels attacks and countermeasures for the designer and the evaluator

Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics

WDDL is Protected against Setup Time Violation Attacks

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