WDDL is Protected against Setup Time Violation Attacks

Selmane, Nidhal; Bhasin, Shivam; Guilley, Sylvain; Graba, Tarik; Danger, Jean‐Luc

doi:10.1109/fdtc.2009.40

Cited by 41 publications

(25 citation statements)

References 25 publications

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“…However, it has been noticed that these styles can also natively withstand some perturbation attacks [57], [58], [73], [11]. It has already been underlined in Sec.…”

Section: Dual-rail With Precharge Logic As Amentioning

confidence: 81%

Fault Injection Resilience

Guilley

Sauvage

Danger

et al. 2010

2010 Workshop on Fault Diagnosis and Tolerance in Cryptography

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Abstract-Fault injections constitute a major threat to the security of embedded systems. Errors occurring in the cryptographic algorithms have been shown to be extremely dangerous, since powerful attacks can exploit few of them to recover the full secrets. Most of the resistance techniques to perturbation attacks have relied so far on the detection of faults. We present in this paper another strategy, based on the resilience against fault attacks. The core idea is to allow an erroneous result to be outputted, but with the assurance that this faulty information conveys no information about the secrets concealed in the chip. We first underline the benefits of FIR: false positive are never raised, secrets are not erased uselessly in case of uncompromising faults injections, which increases the card lifespan if the fault is natural and not malevolent, and FIR enables a high potential of resistance even in the context of multiple faults. Then we illustrate two families of fault injection resilience (FIR) schemes suitable for symmetric encryption. The first family is a protocollevel scheme that can be formally proved resilient. The second family mobilizes a special logic-level architecture of the cryptographic module. We notably detail how a countermeasure of this later family, namely dual-rail with precharge logic style, can both protect both against active and passive attacks, thereby bringing a combined global protection of the device. The cost of this logic is evaluated as lower than detection schemes. Finally, we also give some ideas about the modalities of adjunction of FIR to some certification schemes.

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“…However, it has been noticed that these styles can also natively withstand some perturbation attacks [57], [58], [73], [11]. It has already been underlined in Sec.…”

Section: Dual-rail With Precharge Logic As Amentioning

confidence: 81%

Fault Injection Resilience

Guilley

Sauvage

Danger

et al. 2010

2010 Workshop on Fault Diagnosis and Tolerance in Cryptography

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“…To suppress the increased transient power consumption during fault occurrence, the equalizer circuit [13] proposed in recent years may be effective. Regarding (3), the DFA countermeasure method [14][15][16] is considered to be effective.…”

Section: E Countermeasuresmentioning

confidence: 99%

Information Leakage Threats for Cryptographic Devices Using IEMI and EM Emission

Nakamura

Hayashi

Mizuki

et al. 2018

IEEE Trans. Electromagn. Compat.

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Abstract-In this paper, we present a new information leakage threat combining intentional electromagnetic interference (IEMI) and observations of EM leakage. In previous studies, the analysis of secret key information in cryptographic modules using fault injection has led to methods whereby faults can be injected via low-voltage IEMI. However, the timing of fault injections cannot be controlled with this approach, and it is difficult to obtain faulty ciphertexts for use in secret key analysis by differential fault analysis (DFA). To overcome this problem, we propose a method for estimating the fault injection timing by detecting characteristic fluctuations in the EM leakage from the device. As a result, it may be possible to implement a realistic secret information analysis method applicable to a wide range of devices. First, to show the feasibility of the proposed method, we describe an experiment using an on-chip fault injection circuit that can control the injection timing. Furthermore, we apply a fault analysis method that combines the injection timing estimation method and fault injection by IEMI in a practical experimental environment. We select useful faulty ciphertexts using the proposed method, and then perform secret key analysis by DFA. Experimental results demonstrate that the secret key can be successfully analyzed.

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“…The article [19] shows that WDDL is immune against multiple asymmetric faults such as those caused by setup violations. Basically, the idea is that asymmetric faults turn a VALID token into a NULL one.…”

Section: B Early Evaluation Prevention and Faults Transformationsmentioning

confidence: 99%

“…However, the NULL wave propagation acts as an eraser, which means that the outputs have eventually lost any information about the faulted values. A parallel is done in [19] between asymmetrical faults and the logical propagation of 'U' value in the 9-valued type std_ulogic of VHDL (IEEE standard number 1076).…”

Section: B Early Evaluation Prevention and Faults Transformationsmentioning

confidence: 99%

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Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow

Bhasin

Danger

Flament

et al. 2009

2009 International Conference on Reconfigurable Computing and FPGAs

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Abstract-The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customarily employed by malevolent adversaries: observation and perturbation attacks, also called SCA and DFA in the abundant scientific literature on this topic. Numerous research efforts have been carried out to defeat respectively SCA or DFA. However, few publications deal with concomitant protection against both threats. The current consensus is to devise algorithmic countermeasures to DFA and subsequently to synthesize the DFA-protected design thanks to a DPA-resistant CAD flow. In this article, we put to the fore that this approach is the best neither in terms of performance nor of relevance. Notably, the contribution of this paper is to demonstrate that the strongest SCA countermeasure known so far, namely the dual-rail with precharge logic styles that do not evaluate early (EE), happen surprisingly to be almost natively immune to most DFAs. Therefore, unexpected two-inone solutions against SCA and DFA indeed exist and deserve a closer attention, because they ally simplicity with efficiency. In particular, we illustrate a logic style, called WDDL w/o EE, and a design flow that realizes in practice one possible combined DPA and DFA counter-measure especially suited for reconfigurable hardware.

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WDDL is Protected against Setup Time Violation Attacks

Cited by 41 publications

References 25 publications

Fault Injection Resilience

Fault Injection Resilience

Information Leakage Threats for Cryptographic Devices Using IEMI and EM Emission

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow

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