Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics

Abstract

FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally gave evidence that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, so far, this gain turned out to be lower for FPGAs than for ASICs. The solutions demonstrated in this article exploit the dual-output of modern FPGAs to achieve a better balance of dual-rail interconnections. However, we expect that an in-depth analysis of routing resources power consumption could still help reduce the interconnect differential leakage.

Private circuits II versus fault injection attacks

“…A previous work showed that having the pair of wires pass through the same LUT (by exploiting their dual outputs) can significantly reduce the unbalance [23]. Indeed, the "graph" for both wires is the same.…”

Review of gate‐level differential power analysis and fault analysis countermeasures

“…Similar to the iWDDL approach there is another called divided backend WDDL (DBWDDL) [40] that utilises XOR gates as inverters instead of registers. To ensure balanced routing, one may use dual-output programmable blocks within some FPGA as discussed in [41]. The results of an ASIC implementation of AES algorithm protected with balanced WDDL can be found in [32].…”

Security Enhancement of Remote FPGA Devices By a Low Cost Embedded Network Processor

“…Each of these is a fundamental operation with easily understood formal properties, yet they mapped cleanly and efficiently to a wide variety of reconfigurable devices. In the same year, Laurent Sauvage et al [13] experimentally gave evidence that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, so far, this gain turned out to be lower for FPGAs than for ASICs.…”