Evaluation of pausible clocking for interfacing high speed IP cores in GALS framework

Mekie, Joycee; Chakraborty, Supratik; Sharma, Dinesh K.

doi:10.1109/icvd.2004.1260978

Cited by 15 publications

(14 citation statements)

References 6 publications

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“…However, reliable operation over extended periods of time, despite the inherent risk of meta-stability, still needs to be demonstrated. In [15], the authors comment that previously proposed schemes [16] do not scale well for high clock frequencies of locally synchronous (LS) components and multiple cycle delay in clock distribution due to large clock buffer trees. Due to the presence of large clock buffer trees in the LS components, the assumption of previous schemes of data transfer being stalled within one clock cycle of pausing the sender clock does not hold and leads to extra transmissions in what the authors call the 'clock overrun window', which denotes the skew between pausing the clock and actual stopping of data transmission by the sender module.…”

Section: Pausable Clock Interfacing Schemesmentioning

confidence: 99%

“…In [15], transistor level sender and receiver interface circuits are given and the models are verified by SPICE simulation. The timing analysis of the interface circuits proves that under certain circumstances of bad signal timings of the signal with respect to sender and receiver clock, the synchronisation circuit would fail with a small probability of failure, thus improving on previous schemes.…”

Section: Pausable Clock Interfacing Schemesmentioning

confidence: 99%

See 1 more Smart Citation

Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

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Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.

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Section: Pausable Clock Interfacing Schemesmentioning

confidence: 99%

Section: Pausable Clock Interfacing Schemesmentioning

confidence: 99%

Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

View full text Add to dashboard Cite

show abstract

“…In addition, more complex low-latency synchronizers that employ stoppable and locally-delayed clocks are also applicable for the asynchronous case [10]- [17]. They must take into account additional latency due to clock tree delays [17]- [19], may require non-standard gates, incur timing assumptions and may be restricted to a certain range of clock rates. Therefore, some applications must resort to the family of two-flop synchronizers, discussed in this paper.…”

Section: Introductionmentioning

confidence: 99%

Fast Universal Synchronizers

Dobkin

Ginosar

2009

Lecture Notes in Computer Science

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Abstract.Synchronization circuits are essential in multi-clock-domain systems-on-chip. The most well-known synchronizer consists of two sequentially connected flip-flops that should eliminate the propagation of metastability into the receiver clock domain. We first clarify how such a simple "two-flop" synchronizer can be used in the system, and analyze its performance, showing that the data cycle may be as long as 12 clock cycles. Novel faster synchronizers are described next and their use and improved performance are explained. The fast synchronizer enable shorter data cycles, measuring only 2 to 4 clock cycles. Synchronizer performance is also analyzed when the two communicating clock domains are separated by long interconnect, incurring additional latencies.

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“…Another approach to GALS systems is the use of asynchronous FIFOs [2,3], and this results in overheads in both area and power. In recent years, an alternative method to GALS design, which is mainly based on pausible local clocks, has been developed [4,5,6,7,8,9,10,11,12]. Communication between asynchronous modules is achieved using a pair of request-acknowledge handshaking signals, and the local clocks are paused and stretched, if necessary, to avoid metastability in data transfer.…”

Section: Introductionmentioning

confidence: 99%

Analysis and optimization of pausible clocking based GALS design

Fan

Krstić

Grass

2009

2009 IEEE International Conference on Computer Design

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-Pausible clocking based globally-asynchronous locally-synchronous (GALS) system design has been proven a promising approach to SoCs and NoCs. In this paper, we analyze the throughput reduction and synchronization failures introduced by the widely used pausible clocking scheme, and propose an optimized scheme for higher throughput and more reliable GALS design. The local clock generator is improved to minimize the acknowledge latency, and a novel input port is applied to maximize the safe timing region for the clock tree insertion. Simulation results using the IHP 0.13-µm standard CMOS process demonstrate that up to one-third increase in data throughput and an almost doubled safe timing region for clock tree distribution can be achieved in comparison to the traditional pausible clocking scheme.

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Evaluation of pausible clocking for interfacing high speed IP cores in GALS framework

Abstract: Abstract

Cited by 15 publications

References 6 publications

Asynchronous on-chip networks

Asynchronous on-chip networks

Fast Universal Synchronizers

Analysis and optimization of pausible clocking based GALS design

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