Evaluation of Non-Volatile Memory Based Last Level Cache Given Modern Use Case Behavior

Hankin, Alexander; Shapira, Tomer; Sangaiah, Karthik; Lui, Michael; Hempstead, Mark

doi:10.1109/iiswc47752.2019.9042051

Cited by 9 publications

(4 citation statements)

References 39 publications

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“…While SRAM stores (maintains) data based on a latch-based feedback circuit using 6 transistors, MRAM stores data using magnetic tunnel junction (MTJ) with negligible standby power, compared to the SRAM; the data in the MTJ can be accessed by using an access transistor. Due to the smaller number of transistors, MRAM cells lead to much smaller dynamic and leakage power than SRAM cells [13]. By exploiting the advantages of MRAM, researchers have proposed MRAM-based caches.…”

Section: B Non-volatile Memory (Nvm)mentioning

confidence: 99%

“…Thus, we consider an MRAM model proposed by Jan et al [16]. According to [13], though there are several MRAM models that can be used with NVSim, the Jan's MRAM model [16] is the most energy-efficient compared to the other MRAM models, while it consumes slightly larger area. Note we assume 8-way associative 256KB SRAM arrays as our baseline L2 cache.…”

Section: A M3d-based Sram/mram Hybrid Memorymentioning

confidence: 99%

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Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

Gong

2021

IEEE Access

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Monolithic 3D (M3D) integration has been emerged as a promising technology for finegrained 3D stacking. As the M3D integration offers extremely small dimension of via in a nanometer-scale, it is beneficial for small microarchitectural blocks such as caches, register files, translation look-aside buffers (TLBs), etc. However, since the M3D integration requires low-temperature process for stacked layers, it causes lower performance for stacked transistors compared to the conventional 2D process. In contrast, non-volatile memory (NVM) such as magnetic RAM (MRAM) is originally fabricated at a low temperature, which enables the M3D integration without performance degradation. In this paper, we propose an energy-efficient unified L2 TLB-cache architecture exploiting M3D-based SRAM/MRAM hybrid memory. Since the M3D-based SRAM/MRAM hybrid memory consumes much smaller energy than the conventional 2D SRAM-only memory and 2D SRAM/MRAM hybrid memory, while providing comparable performance, our proposed architecture improves energy efficiency significantly. Especially, as our proposed architecture changes the memory partitioning of the unified L2 TLB-cache depending on the L2 cache miss rate, it maximizes the energy efficiency for parallel workloads suffering extremely high L2 cache miss rate. According to our analysis using PARSEC benchmark applications, our proposed architecture reduces the energy consumption of L2 TLB+L2 cache by up to 97.7% (53.6% on average), compared to the baseline with the 2D SRAM-only memory, with negligible impact on performance. Furthermore, our proposed technique reduces the memory access energy consumption by up to 32.8% (10.9% on average), by reducing memory accesses due to TLB misses.

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Section: B Non-volatile Memory (Nvm)mentioning

confidence: 99%

Section: A M3d-based Sram/mram Hybrid Memorymentioning

confidence: 99%

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

Gong

2021

IEEE Access

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“…Improved density and energy efficiency could revolutionize general-purpose on-chip storage, and recent efforts have endeavored to replace high-performance memories, like caches, with eNVM-based alternatives [56,63,73]. However, caches must handle a large volume of writes depending on the application, so the achievable write latency and endurance per eNVM comes to the forefront of design considerations.…”

Section: Non-volatile Llc Solutionsmentioning

confidence: 99%

“…On the other hand, the need for optimized on-chip storage solutions and memory innovation applies both to specialized hardware accelerators and for general-purpose CPU systems as well. More broadly, prior works have unveiled incredible potential improvements in storage density and energy efficiency by employing eN-VMs across various architecture domains [56,63,115]. With many publications showcasing the benefits of eNVM storage technologies, it is critical for system designers to be able to explore their varying capabilities and empower efficient future on-chip storage.…”

Section: Introductionmentioning

confidence: 99%

NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories

Pentecost¹,

Hankin²,

Donato³

et al. 2021

Preprint

Self Cite

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Repeated off-chip memory access to DRAM drive up operating power for data-intensive applications, and SRAM technology scaling and leakage power limits the efficiency of embedded memories. Future on-chip storage will need higher density and energy efficiency, and the actively expanding field of emerging, embeddable non-volatile memory (eNVM) technologies is providing many potential candidates to satisfy this need. Each technology proposal presents distinct trade-offs in terms of density, read, write, and reliability characteristics, and we present a comprehensive framework for navigating and quantifying these design trade-offs alongside realistic system constraints and application-level impacts. This work evaluates eNVM-based storage for a range of application and system contexts including machine learning on the edge, graph analytics, and general purpose cache hierarchy, in addition to describing a freely available (http://nvmexplorer.seas.harvard.edu/) set of tools for application experts, system designers, and device experts to better understand, compare, and quantify the next generation of embedded memory solutions.

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Efficient Deep Learning Using Non-volatile Memory Technology in GPU Architectures

Inci,

Isgenc,

Marculescu

2023

Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing

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Evaluation of Non-Volatile Memory Based Last Level Cache Given Modern Use Case Behavior

Cited by 9 publications

References 39 publications

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories

Efficient Deep Learning Using Non-volatile Memory Technology in GPU Architectures

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