Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

Abstract

Monolithic 3D (M3D) integration has been emerged as a promising technology for finegrained 3D stacking. As the M3D integration offers extremely small dimension of via in a nanometer-scale, it is beneficial for small microarchitectural blocks such as caches, register files, translation look-aside buffers (TLBs), etc. However, since the M3D integration requires low-temperature process for stacked layers, it causes lower performance for stacked transistors compared to the conventional 2D process. In contrast, non-volatile memory (NVM) such as magnetic RAM (MRAM) is originally fabricated at a low temperature, which enables the M3D integration without performance degradation. In this paper, we propose an energy-efficient unified L2 TLB-cache architecture exploiting M3D-based SRAM/MRAM hybrid memory. Since the M3D-based SRAM/MRAM hybrid memory consumes much smaller energy than the conventional 2D SRAM-only memory and 2D SRAM/MRAM hybrid memory, while providing comparable performance, our proposed architecture improves energy efficiency significantly. Especially, as our proposed architecture changes the memory partitioning of the unified L2 TLB-cache depending on the L2 cache miss rate, it maximizes the energy efficiency for parallel workloads suffering extremely high L2 cache miss rate. According to our analysis using PARSEC benchmark applications, our proposed architecture reduces the energy consumption of L2 TLB+L2 cache by up to 97.7% (53.6% on average), compared to the baseline with the 2D SRAM-only memory, with negligible impact on performance. Furthermore, our proposed technique reduces the memory access energy consumption by up to 32.8% (10.9% on average), by reducing memory accesses due to TLB misses.

Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies

“…The Stealth-Persist structure improved the performance of persistent applications by 42.02%. Y-Ho et al [18] proposed the SRAM/MRAM as the L2 cache, which used the cache miss rate for diferent memory conigurations in the system controller. The scheme reduced miss rates of SRAM and improved energy eiciency.…”

Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache

“…Gong [17] has designed a SRAM/MRAM hybrid TLB-Cache that makes use of monolithic 3D integration of non-voltatile memories. This work looks to increase the capacity and decrease the power consumption of the cache by leveraging similar techniques to our main memory system.…”

Improved Ferroelectricity and Endurance of Hf0.5Zr0.5O2 Thin Films in Low Thermal Budget with Novel Bottom Electrode Doping Technology

“…[1,2] A series of new material-based memory devices, such as resistive-RAM, magnetic-RAM, and ferroelectric-RAM, and a number of novel integration methods, such as through silicon vias (TSV)-based 3D integration and M3D integration have been implemented to greatly enhance the performance and energy-efficiency of hardware in IMC or NMC. [2][3][4] Combining novel ferroelectric memory devices with M3D integration is expected to provide a revolutionary approach to achieve high performance and low power-consumption IMC or NMC integrated circuits (ICs) with high-bandwidth data communication ability and highly reduced chip area. [5] Ferroelectric memory has attracted considerable research and development interest due to its potential to operate at higher speed with lower power consumption compared to conventional flash memory.…”