Evaluation of interface traps inside the conduction band of InAs-on-insulator nMOSFET by self-consistent Hall-QSCV method

Abstract

Interface trap density (Dit) inside the conduction band of (111)-oriented InAs-on-insulator (InAs-OI) n-channel metal-oxide-semiconductor field-effect-transistor (nMOSFET) was experimentally evaluated by developing a method through a combination of a Hall measurement and quasi-static split C–V (Hall-QSCV). The surface potential and Dit of the InAs-OI nMOSFET were self-consistently calculated by numerically solving the Schrödinger–Poisson equation. The energy distributions of Dit were found to be almost independent of the ultra-thin-body channel thickness and the quantization energy, indicating the validity of the proposed Hall-QSCV evaluation. The energy position of the Dit minimum is in good agreement with the theoretically predicted position of the charge neutrality level, which locates deeply inside the conduction band of InAs. The experimental maximum surface electron density Nsmax at the InAs MOS interface, limited by Fermi level pinning, is 1.2 × 1013 cm−2, which is 2–3 times higher than Nsmax at the In0.53Ga0.47As MOS interfaces, owing to the lower Dit inside the InAs conduction band.

(Invited) Physical Understanding of HfZrO2/Si FeFET Memory and Its AI Applications

“…2, a 2-terminal P-V measurement for a FeFET with the source, drain, and substrate grounded as a semiconductor terminal allows us to provide the ECS Transactions, 112 (1) 65-74 (2023) information of P [10]. On the other hand, the total areal charges of qNs and qNtrap can be evaluated by using a quasi-static split C-V method [7,11]. It is well known that Ns can be determined by the conventional split C-V method using a small signal AC voltage, only when traps and interface states can be ignored.…”

“…On the other hand, Ns can be directly evaluated by Hall measurements of FeFETs with Hall bars. Thus, we can estimate Ntrap by subtracting the Ns values obtained by Hall measurements from the areal charge density determined by quasi-split C-V [7,[11][12][13]. As a result, we can quantify the contribution of traps on FeFET memory operation.…”

Accurate evaluation of interface trap density at InAs MOS interfaces by using C–V curves at low temperatures

“…[1][2][3][4][5][6][7] InAs is also promising for photodiodes (PDs) in the near-infrared region because of its narrow band gap, superior avalanche multiplication gain, and low excess noise. [8][9][10][11] However, the InAs MOS channel has the problem of high interface trap density (D it ) at high-k/InAs interfaces, [12][13][14][15][16][17][18][19] which significantly degrades the performance of MOSFETs and PDs, such as reliability, drive current, dark current, and subthreshold swing. Therefore, a fabrication method to reduce the high D it is required, indicating the importance of the accurate evaluation of D it values.…”

“…For issue (2), the Fermi level tends to be located inside the conduction band at low temperatures for InAs because of the considerably low DOS of electrons. 19,24) Therefore, the Boltzmann distribution should be inaccurate for simulating electron concentrations in the InAs band structure, while the Boltzmann distribution is used to simplify the calculation. Therefore, in this study, the impact of the choice of the distribution function on D it evaluated by the Terman method was examined.…”