Evaluation of compensation techniques for CMOS operational amplifier design

Zaidi, Muhaned; Grout, Ian; A’ain, Abu Khari

doi:10.1109/icicdt.2018.8399722

Cited by 3 publications

(3 citation statements)

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“…Low-voltage Low-power Bulk-driven CMOS Op-Amp Using Negative Miller for ECG with the second stage [14], resulting in a two-stage bulk-driven CMOS op-amp, which is commonly known to have two poles [22,23]. The Miller compensation technology moves the first low-frequency pole (p1) to the origin (to the lower frequency), which makes the pole more dominant.…”

Section: Standard Miller Compensationmentioning

confidence: 99%

“…The parasitic capacitances are caused by the transistor well and substrate structure. In Figure 7, the Cbd capacitance provides feedback between the bulk (input node) and the drain (output node) [14].…”

Section: Muhaned Zaidimentioning

confidence: 99%

“…Miller compensation or Miller capacitance is a technique used in many op-amp designs to improve the stability (phase margin PM) in a closed loop configuration. However, it causes reduction of the frequency response, so the input node and the output node are connected with a normal capacitor (Cc) [11,13,14], creating Miller compensation. Another compensation technique is negative Miller compensation, which is utilized to improve UGF by reducing or…”

Section: Introductionmentioning

confidence: 99%

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Low-voltage Low-power Bulk-driven CMOS Op-Amp Using Negative Miller Compensation for ECG

Zaidi¹

2022

J. Eng. Technol. Sci.

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Two bulk-driven CMOS (Complementary Metal Oxide Semiconductor) operational amplifier (op-amp) designs for electrocardiogram (ECG) application are presented and compared in this paper. Both op-amps are based on two-stage amplification, where bulk-driven differential input is the first stage, while additional DC gain is the second stage. Different compensation techniques were integrated in each op-amp design. Standard Miller compensation was used for the first op-amp parallel with the second stage. The novelty of the second op-amp is that it utilizes negative Miller compensation between the bulk-driven input node and the output node of the first stag, while standard Miller compensation was used in the second stage. The purpose of this work was to compare DC gain, phase margin (PM) and unit gain frequency (UGF) obtained through different simulated compensation strategies and test results. The op-amps were simulated using 0.25 μm CMOS technology. The simulation results are presented using the standard model libraries from Tanner EDA tools, operating on a single rail +0.8V power supply.

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Section: Standard Miller Compensationmentioning

confidence: 99%

Section: Muhaned Zaidimentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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