Evaluating the efficiency of DSP Block synthesis inference from flow graphs

ACM Trans. Reconfigurable Technol. Syst.

et al. 2014

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DSP blocks in modern FPGAs can be used for a wide range of arithmetic functions, offering increased performance while saving logic resources for other uses. They have evolved to better support a plethora of signal processing tasks, meaning that in other application domains they may be underutilised. The DSP48E1 primitives in new Xilinx devices support dynamic programmability that can help extend their usefulness; the specific function of a DSP block can be modified on a cycle-by-cycle basis. However, the standard synthesis flow does not leverage this flexibility in the vast majority of cases. The lean DSP Extension Architecture (iDEA) presented in this article builds around the dynamic programmability of a single DSP48E1 primitive, with minimal additional logic to create a general-purpose processor supporting a full instruction-set architecture. The result is a very compact, fast processor that can execute a full gamut of general machine instructions. We show a number of simple applications compiled using an MIPS compiler and translated to the iDEA instruction set, comparing with a Xilinx MicroBlaze to show estimated performance figures. Being based on the DSP48E1, this processor can be deployed across next-generation Xilinx Artix-7, Kintex-7, Virtex-7, and Zynq families.

Section: Introductionmentioning

confidence: 99%

The iDEA DSP Block-Based Soft Processor for FPGAs

Cheah

Brosser

ACM Trans. Reconfigurable Technol. Syst.

et al. 2014

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“…Dedicated DSP Blocks which are able to implement operations such as multiplication or multiply-accumulate in a fast and efficient manner are provided in modern FPGA and they are used to build squarers in the literature [6]- [8]. To use them efficiently, designs must be customised to the datapath of the DSP block [9]. Since they are large and limited in number, reducing the number of DSP blocks required for elementary operations like squaring can facilitate the mapping of larger designs to an FPGA.…”

Section: Introductionmentioning

confidence: 99%

Efficient Large Integer Squarers on FPGA

Xu¹,

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

McLoughlin

2013

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This paper presents an optimised high throughput architecture for integer squaring on FPGAs. The approach reduces the number of DSP blocks required compared to a standard multiplier. Previous work has proposed the tiling method for double precision squaring, using the least number of DSP blocks so far. However that approach incurs a large overhead in terms of look-up table (LUT) consumption and has a complex and irregular structure that is not suitable for higher word size. The architecture proposed in this paper can reduce DSP block usage by an equivalent amount to the tiling method while incurring a much lower LUT overhead: 21.8% fewer LUTs for a 53-bit squarer. The architecture is mapped to a Xilinx Virtex 6 FPGA and evaluated for a wide range of operand word sizes, demonstrating its scalability and efficiency.

“…For polynomial evaluation, the basic functions of multiplication and squaring can be efficiently built using DSP blocks. In order to obtain maximum performance, it is important to consider the structure of the DSP block when building a computational datapath [27]. Fast, wide multipliers are built by cascading together chains of DSP blocks using dedicated hard wires that do not add significantly to the routing delay.…”

Section: Fpga Computationmentioning

confidence: 99%

Square-rich fixed point polynomial evaluation on FPGAs

Xu¹,

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

McLoughlin

2014

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Polynomial evaluation is important across a wide range of application domains, so significant work has been done on accelerating its computation. The conventional algorithm, referred to as Horner's rule, involves the least number of steps but can lead to increased latency due to serial computation. Parallel evaluation algorithms such as Estrin's method have shorter latency than Horner's rule, but achieve this at the expense of large hardware overhead. This paper presents an efficient polynomial evaluation algorithm, which reforms the evaluation process to include an increased number of squaring steps. By using a squarer design that is more efficient than general multiplication, this can result in polynomial evaluation with a 57.9% latency reduction over Horner's rule and 14.6% over Estrin's method, while consuming less area than Horner's rule, when implemented on a Xilinx Virtex 6 FPGA. When applied in fixed point function evaluation, where precision requirements limit the rounding of operands, it still achieves a 52.4% performance gain compared to Horner's rule with only a 4% area overhead in evaluating 5 th degree polynomials.