Evaluating STT-RAM as an energy-efficient main memory alternative

Kültürsay, Emre; Kandemir, Mahmut; Sivasubramaniam, Anand; Mutlu, Onur

doi:10.1109/ispass.2013.6557176

Cited by 382 publications

(226 citation statements)

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“…Among various BA-NVM technologies, STT-MRAM has near-SRAM endurance (> 10 15 ) [22,44]. Therefore, endurance is not an issue in our implementation.…”

Section: Discussionmentioning

confidence: 99%

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Byte-addressable nonvolatile memories promise a new technology, persistent memory, which incorporates desirable attributes from both traditional main memory (byte-addressability and fast interface) and traditional storage (data persistence). To support data persistence, a persistent memory system requires sophisticated data duplication and ordering control for write requests. As a result, applications that manipulate persistent memory (persistent applications) have very different memory access characteristics than traditional (non-persistent) applications, as shown in this paper. Persistent applications introduce heavy write traffic to contiguous memory regions at a memory channel, which cannot concurrently service read and write requests, leading to memory bandwidth underutilization due to low bank-level parallelism, frequent write queue drains, and frequent bus turnarounds between reads and writes. These characteristics undermine the high-performance and fairness offered by conventional memory scheduling schemes designed for non-persistent applications.Our goal in this paper is to design a fair and high-performance memory control scheme for a persistent memory based system that runs both persistent and non-persistent applications. Our proposal, FIRM, consists of three key ideas. First, FIRM categorizes request sources as non-intensive, streaming, random and persistent, and forms batches of requests for each source. Second, FIRM strides persistent memory updates across multiple banks, thereby improving bank-level parallelism and hence memory bandwidth utilization of persistent memory accesses. Third, FIRM schedules read and write request batches from different sources in a manner that minimizes bus turnarounds and write queue drains. Our detailed evaluations show that, compared to five previous memory scheduler designs, FIRM provides significantly higher system performance and fairness.

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“…Among various BA-NVM technologies, STT-MRAM has near-SRAM endurance (> 10 15 ) [22,44]. Therefore, endurance is not an issue in our implementation.…”

Section: Discussionmentioning

confidence: 99%

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

Self Cite

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“…The average overhead of a clflush and mfence combined together is reported to be 250ns [14], which makes this approach costly, given that persistent memory access times are expected to be on the order of tens to hundreds of nanoseconds [3,4,7]. 1 The two instructions flush dirty data blocks from the CPU cache to persistent memory and wait for the completeness of all memory writes, and incur high overhead in persistent memory [10,14,32,33].…”

Section: Mitigating the Ordering Overheadmentioning

confidence: 99%

“…Since these technologies have low idle power, high storage density, and good scalability properties compared to DRAM [1,2], they have been regarded as potential alternatives to replace or complement DRAM as the technology used to build main memory [3,4,5,6,7,8,9]. Perhaps even more importantly, the non-volatility property of these emerging technologies promises to enable memory-level storage (i.e., persistent memory), which can store data persistently at the main memory level at low latency [10,11,12,13,14,15,16].…”

Section: Introduction Emerging Non-volatile Memory (Nvm) Technologmentioning

confidence: 99%

“…Therefore, in order to preserve persistence ordering from the CPU cache to persistent memory, software needs to explicitly include the relatively costly cache flush (e.g., clflush) and memory fence (e.g., mfence) instructions (at the end of each transaction) to force the ordering of cache writebacks [11,13,14,15]. The average overhead of a clflush and mfence combined together is reported to be 250ns [14], which makes this approach costly, given that persistent memory access times are expected to be on the order of tens to hundreds of nanoseconds [3,4,7].…”

Section: Introduction Emerging Non-volatile Memory (Nvm) Technologmentioning

confidence: 99%

“…Their DRAM-comparable performance and better-than-DRAM technology-scalability, which can enable high memory capacity at low cost, make these technologies promising alternatives to DRAM [3,4,5]. As such, many recent works examined the use of these technologies as part of main memory [3,4,5,6,7,8,9,10,11,12,13,14,15,16], providing disk-like data persistence at DRAM-like latencies.…”

Section: Introduction Emerging Non-volatile Memory (Nvm) Technologmentioning

confidence: 99%

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Loose-Ordering Consistency for persistent memory

Shu

Sun

et al. 2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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124

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Abstract-Emerging non-volatile memory (NVM) technologies enable data persistence at the main memory level at access speeds close to DRAM. In such persistent memories, memory writes need to be performed in strict order to satisfy storage consistency requirements and enable correct recovery from system crashes. Unfortunately, adhering to a strict order for writes to persistent memory significantly degrades system performance as it requires flushing dirty data blocks from CPU caches and waiting for their completion at the main memory in the order specified by the program. This paper introduces a new mechanism, called Loose-Ordering Consistency (LOC), that satisfies the ordering requirements of persistent memory writes at significantly lower performance degradation than stateof-the-art mechanisms. LOC consists of two key techniques. First, Eager Commit reduces the commit overhead for writes within a transaction by eliminating the need to perform a persistent commit record write at the end of a transaction. We do so by ensuring that we can determine the status of all committed transactions during recovery by storing necessary metadata information statically with blocks of data written to memory. Second, Speculative Persistence relaxes the ordering of writes between transactions by allowing writes to be speculatively written to persistent memory. A speculative write is made visible to software only after its associated transaction commits. To enable this, our mechanism requires the tracking of committed transaction ID and support for multi-versioning in the CPU cache. Our evaluations show that LOC reduces the average performance overhead of strict write ordering from 66.9% to 34.9% on a variety of workloads.

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Storage Class Memory

Burr

Franzon

2014

Emerging Nanoelectronic Devices

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One challenge in computing systems is the need for new memory technologies that can improve overall performance. More and more frequently, the ability of a CPU to rapidly execute programs is being limited by the rate at which data can arrive at the processor. Unfortunately, scaling does not automatically solve this problem. One evolutionary solution has been to increase the size of cache memory and thus the floor space that SRAM occupies on a CPU chip. However, this trend eventually leads to a decrease of the net information throughput.While DRAM offers higher density than SRAM, auxiliary circuitry is required to maintain the stored data. True nonvolatility has conventionally required external storage media (e.g., magnetic Hard Disk Drives (HDDs), optical CDs, etc.), with access times that are slower than the volatile memory by many orders of magnitude. Solid-State Disks (SSDs) based on NAND Flash have recently offered nonvolatility at significantly lower latencies than HDDs, but are block-based, much slower to erase than to program, and offer fairly poor cycle endurance.The development of an electrically accessible nonvolatile memory with high speed, high density, and high endurance, referred to as "Storage Class Memory" or SCM, would initiate a revolution in computer architecture. By using CMOS-compatible fabrication technology scaled beyond the present limits of SRAM and FLASH, such a memory technology could enable breakthroughs in both stand-alone and embedded memory applications. This development could potentially provide a significant increase in information throughput beyond the benefits traditionally associated with scaling CMOS devices into the nanoscale.This chapter is structured as follows. Sections 25.2 and 25.3 motivate and define SCMs. Sections 25.4 through 25.6 discuss target specifications and potential device solutions. Sections 25.7 through 25.10 discuss architectural implications of SCMs and open issues related to architectural exploitation.

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Evaluating STT-RAM as an energy-efficient main memory alternative

Cited by 382 publications

References 64 publications

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Loose-Ordering Consistency for persistent memory

Storage Class Memory

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