Evaluating Au and Pd contacts in mono and multilayer MoS<inf>2</inf> transistors

Abstract

The search of a p-type metal contact on MoS2 has remained inconclusive, with high work-function metals such as Au, Ni and Pt showing n-type behavior [1] and mixed reports of n as well as p-type behavior for Pd. In this work we report for the first time, quantitative band alignment of Pd and Au-MoS2 interfaces using low temperature and scanning photocurrent measurements on MoS2 transistors with varying metal contacts (Au-Au, Pd-Pd and Au-Pd). Our results indicate n-type behavior for Pd contacts on multilayer as well as monolayer MoS2 b) of nearly 0.5 eV, four times that for Au contacts indicating that the MoS2 Fermi-level is pinned in the upper half of MoS2 bandgap. Molybdenum disulphide (MoS2) has emerged as an attractive candidate for future CMOS applications owing to its graphenelike 2D nature but with a bandgap of nearly 1.2 eV (for multilayer MoS2). High on/off current ratios with sub-threshold slope ~60 mV/decade and high mobility (>100 cm 2 /Vs) have been reported [1][2][3]. The n/p type behavior of MoS2 transistors is controlled by the contacts (electron vs hole injection). Till date p-type MoS2 transistors have been difficult to demonstrate due to the n-type behavior of high workm) metals on MoS2 [1]. However some recent reports of Pd contacts have reported n as well as p-type behavior [4-7] ( Table 1). In this work we have fabricated back-gated (p + -Si/SiO2 300 nm) transistors on exfoliated MoS2 flakes consisting of a single as well as ~20 stacked layers of MoS2. An optical image and a schematic of a fabricated device are shown in Figures 1(a) and (b). Source/drain contacts with different metal configurations (Au-Au, Pd-Pd and Au-Pd) were fabricated using e-beam lithography and e-beam evaporation. Figure 1(c) shows the alignment of Au and Pd work-function with MoS2 energy bands in free and in contact mode. Figures 1(d) and (e) show the Raman and XPS spectroscopy signatures of monolayer MoS2 measured on fabricated devices respectively. For multilayer flakes, AFM (not shown) measurements were carried out to estimate the number of device layers (~20). Figures 2 and 3 show the ID-VD characteristics of multi and monolayer MoS2 at fixed Vgs indicating (a) different Schottky barrier heights for Au and Pd due to the asymmetric nature of the Aub for Pd/MoS2 interface vs Au due to the higher resistance of the Pd-Pd device. Figure 4 shows the ID-VG transfer characteristics indicating the n-type behavior of Au and Pd contacts irrespective of the thickness of the MoS2 channel layer. Figures 5 and 6 show variable temperature ID-VG and Arrhenius plots (ID vs 1000/T) for the Au-MoS2-Au device respectively. Similar measurements on Pd devices were used to extract the Pd/MoS2 and Au/MoS2 b GS plots as shown in Figure 7 [1]. The effective b for Pd/MoS2 is 0.5 eV, nearly four times that for the Au/MoS2 interface (0.12 eV). Inspite of the b, Pd makes an n-type contact on MoS2, since the band gap for bulk MoS2 is 1.2 eV. Scanning photocurrent microscopy on Au-Au and Au-Pd devices ( Figure 8) further helps to identify the rela...

Improved Contacts to MoS2 Transistors by Ultra-High Vacuum Metal Deposition

“…The latter effect is more pronounced if μC < μ, as shown in Figure 2e and discussed below. Figure 2f reveals the measured temperature dependence of the regular Ni and the cleanest Au contacts, which can be best fitted using our model with ΦB = 150 meV (consistent with previous measurements for Ni and Au contacts 22,34 ) and μC0 = 0.25 and 20 cm 2 V -1 s -1 , respectively.…”

“…Thus we take Φ B = 150 meV for Ni and Au contacts, which has been measured elsewhere. 1,2 An in-depth discussion of Φ B extractions from Schottky barrier FETs can be found elsewhere.…”

“…The pinning results in a small Schottky barrier for electrons, taken to be Φ B = 150 meV for Ni and Au contacts. 1,2 The specific interfacial resistivity is ρ i = ∂V/∂J| V=0 , which describes solely interfacial resistance (between the top MoS 2 layer and the metal) and can therefore be smaller than the contact resistivity (ρ C ) which includes contributions from regions immediately above and below the interface. 4,5 Thus while ρ C ≥ ρ i (see Figure S10) we use ρ i to calculate R C vs. T for simplicity since the determination of ρ C requires prior knowledge of the inter-layer (between layers) transport underneath the contact.…”

“…In order to achieve field-effect transistor (FET) gate lengths below 10 nm, transistor channel thicknesses below approximately 2 nm are required to maintain good gate control of the channel and to minimize leakage current. 1,2 In such thin films, 3-dimensional (3D) semiconductors like Si suffer from surface roughness (SR) effects: SR scattering reduces their mobility by nearly two orders of magnitude [3][4][5][6][7][8] and SR fluctuations (coupled with increases of band gap due to quantization effects 9 ) can lead to strong variability in threshold voltage. 10,11 In contrast, when sufficiently clean, 2-dimensional (2D) materials such as graphene and MoS2 do not have surface roughness and exhibit good electrical mobility that is largely independent of channel thickness.…”

“…Since the measured I D of our devices is limited by gate leakage for V G ≪ V T , we cannot extract Φ B for a larger range of E N that reaches the flat-band voltage, preventing an accurate estimate of ϕ eff . Thus we take Φ B = 150 meV for Ni and Au contacts, which has been measured elsewhere 1,2. An in-depth discussion of Φ B extractions from Schottky barrier FETs can be found elsewhere 3.…”