The scaling of transistors to sub-10 nm dimensions is strongly limited by their contact resistance (RC). Here we present a systematic study of scaling MoS2 devices and contacts with varying electrode metals and controlled deposition conditions, over a wide range of temperatures (80 to 500 K), carrier densities (10(12) to 10(13) cm(-2)), and contact dimensions (20 to 500 nm). We uncover that Au deposited in ultra-high vacuum (∼10(-9) Torr) yields three times lower RC than under normal conditions, reaching 740 Ω·μm and specific contact resistivity 3 × 10(-7) Ω·cm(2), stable for over four months. Modeling reveals separate RC contributions from the Schottky barrier and the series access resistance, providing key insights on how to further improve scaling of MoS2 contacts and transistor dimensions. The contact transfer length is ∼35 nm at 300 K, which is verified experimentally using devices with 20 nm contacts and 70 nm contact pitch (CP), equivalent to the "14 nm" technology node.

We report the experimental demonstration of Fermi level depinning using nickel oxide (NiO) as the insulator material in metal-insulator-semiconductor (M-I-S) contacts. Using this contact, we show less than 0.1 eV barrier height for holes in platinum/NiO/silicon (Pt/NiO/p-Si) contact. Overall, the pinning factor was improved from 0.08 (metal/Si) to 0.26 (metal/NiO/Si). The experimental results show good agreement with that obtained from theoretical calculation. NiO offers high conduction band offset and low valence band offset with Si. By reducing Schottky barrier height, this contact can be used as a carrier selective contact allowing hole transport but blocking electron transport, which is important for high efficiency in photonic applications such as photovoltaics and optical detectors.

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