Estimation of NAND Flash Memory Threshold Voltage Distribution for Optimum Soft-Decision Error Correction

Lee, Donghwan; Sung, Wonyong

doi:10.1109/tsp.2012.2222399

Cited by 82 publications

(72 citation statements)

References 20 publications

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“…However, advanced process technology itself is no more sufficient to increase the density of NAND flash memory because scaling also lowers the quality of threshold voltage signal sensed from memory cells. As the feature size of memory cells reduces, not only the number of electrons stored at each floating-gate diminishes but also This paper summarizes the key results in our previous publications [1][2][3], and shows the overall performance when combining all these techniques. This work was supported by the Brain Korea 21 Project and the National Research Foundation of Korea (NRF) grants funded by the Ministry of Education, Science and Technology (MEST), Republic of Korea (No.…”

Section: Introductionmentioning

confidence: 77%

“…The threshold voltage distribution of NAND flash memory changes continuously according to the data retention time and the number of PE cycles. We have developed a parameter estimation algorithm to offer statistical information of the threshold voltage signal to ECC decoders and signal processing units [1]. We also explain an efficient CCI cancellation scheme that employs a least squares based algorithm for fast convergence [2].…”

Section: Introductionmentioning

confidence: 99%

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Signal processing techniques for reliability improvement of sub-20NM NAND flash memory

Lee

Kim

Sung

2013

SiPS 2013 Proceedings

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The capacity of NAND flash memory has been continuously increased by adopting process technology scaling and multi-level cell (MLC) data coding. However, the reliability of stored data becomes a very important issue because the scaled feature size lowers the number of electrons at each floating-gate while increasing the cell-to-cell interference. In this paper, we review recent advances in signal processing techniques for reliability improvement of sub-20 nm NAND flash memory, which includes estimation of the threshold voltage distribution, cell-to-cell interference cancellation, and optimal multi-level memory sensing. We also present experimental results for the explained signal processing algorithms. Especially, we demonstrate the reliability improvement when combining all these techniques.

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Section: Introductionmentioning

confidence: 77%

Section: Introductionmentioning

confidence: 99%

Signal processing techniques for reliability improvement of sub-20NM NAND flash memory

Lee

Kim

Sung

2013

SiPS 2013 Proceedings

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“…The NAND Flash memory channel estimation proposed in [22] was used to decide the SRVs and the smallest output precision was chosen among the possible decoding schemes. Figure 8 shows the total energy consumption for MSB pages.…”

Section: Low-energy Error Correction Scheme For Nand Flash Memorymentioning

confidence: 99%

“…Another approach is to estimate the signal quality of NAND Flash memory periodically with channel estimation algorithms [22]. By sensing the signal with multiple threshold voltages, we can estimate the mean and the variance of each symbol.…”

Section: Iteration Count-based Precision Selectionmentioning

confidence: 99%

Low-energy error correction of NAND Flash memory through soft-decision decoding

Kim

Sung

2012

EURASIP J. Adv. Signal Process.

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The raw bit error rate of NAND Flash memory increases as the semiconductor geometry shrinks for high density, which makes it very necessary to employ a very strong error correction circuit. The soft-decision-based error correction algorithms, such as low-density parity-check (LDPC) codes, can enhance the error correction capability without increasing the number of parity bits. However, soft-decision error correction schemes need multiple precision data, which obviously increases the energy consumption in NAND Flash memory for more sensing operations as well as more data output. We examine the energy consumption of a NAND Flash memory system with an LDPC code-based soft-decision error correction algorithm. The energy consumed at multiple-precision NAND Flash memory as well as the LDPC decoder is considered. The output precision employed is 1.0, 1.4, 1.7, and 2.0 bits per data. In addition, we also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. The experiment was conducted with 32-nm 128-Gbit 2-bit multi-level cell NAND Flash memory and a 65-nm LDPC decoding VLSI.

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“…Although the two-step trial-and-error procedure significantly reduces the soft-decision memory sensing induced read latency, the decoding throughput degradation is still noticeable especially when the NAND flash memory chip is heavily cycled. As the throughput of LDPC decoding has significant impact on the performance of overall storage system, great effort has been made to investigate the throughput improvement techniques for LDPC decoding [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory

Zhao

Sun

et al. 2014

2014 30th Symposium on Mass Storage Systems and Technologies (MSST)

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Multi-level per cell (MLC) technique significantly improves storage density, but also poses new challenge to data integrity in NAND flash memory. Therefore, low-density parity-check (LDPC) code and soft-decision memory sensing have become indispensable in future NAND flash-based solid state drive design. However, these more powerful technologies inevitably increase the memory read latency and hence degrade the decoding throughput. Motivated by intra-cell unbalanced bit error probability and data dependency in MLC NAND flash memory, this paper proposes two techniques, i.e. intra-cell data placement interleaving and intra-cell data dependency aware min-sum decoding, to effectively improve the throughput of LDPC decoding. Experimental results show that, the proposed techniques used in an integrated way can improve the LDPC decoding throughput by up to 85% when the MLC NAND flash chip is heavily cycled, compared with conventional design practice.

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Estimation of NAND Flash Memory Threshold Voltage Distribution for Optimum Soft-Decision Error Correction

Cited by 82 publications

References 20 publications

Signal processing techniques for reliability improvement of sub-20NM NAND flash memory

Signal processing techniques for reliability improvement of sub-20NM NAND flash memory

Low-energy error correction of NAND Flash memory through soft-decision decoding

Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory

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