Estimation of ground bounce effects on CMOS circuits

Kabbani, A.; Al-Khalili, A.J.

doi:10.1109/iscas.1999.777946

Cited by 11 publications

(11 citation statements)

References 6 publications

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“…Traditionally, ground bounce has been a phenomenon associated with input/output buffers and internal circuitry [7,13]. Recently, this inductive noise problem has also been associated with clock gating [16,28]. Until now, ground bounce noise originating from the power-mode transition of a power-gating structure has not seriously been considered.…”

Section: Introductionmentioning

confidence: 99%

“…3 [18]). This voltage fluctuation-also known as ground bounce-, which is associated with the switching of I/O buffers and internal digital circuitry and clock gating, is one of the growing concerns for the reliability of power delivery in nanoscale systems [7,13,16,28,33]. [13] The use of high-performance logic circuits to increase system performance resulted in increased concern toward ground-bounce, particularly in most CMOS logic circuits.…”

Section: Introduction and Propagation Of Ground-bounce Noise In Powermentioning

confidence: 99%

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An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

Chowdhury

Khaled

Gjanci

2010

Circuits Syst Signal Process

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Leakage has become one of the most dominant factors of power consumption and signal integrity of nanometer-scale integrated circuits. Recently, powergating structures have proven to be effective in controlling leakage. In this paper an alternative dual-V th reduced power-gating structure is proposed for better reduction of leakage currents, especially for low-power and high-performance portable devices. The proposed technique maintains an intermediate power-saving state as well as the conventional power cut-off state. The experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF modes. In addition, an analysis of ground bounce due to power-mode transition in power-gating structures is presented. It is demonstrated that the proposed technique provides a way to control ground bounce during power-mode transition. Due to the presence of the intermediate state, its stepwise turning on feature will provide higher reduction of the magnitudes of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.

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Section: Introductionmentioning

confidence: 99%

Section: Introduction and Propagation Of Ground-bounce Noise In Powermentioning

confidence: 99%

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

Chowdhury

Khaled

Gjanci

2010

Circuits Syst Signal Process

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“…Most of the regulators are usually used to isolate the noise from power supplies [1][2][3][4]. Since the SoC products have been more and more popular recently, to integrate analog and digital circuits into a single chip is very difficult.…”

Section: Introductionmentioning

confidence: 99%

A new current-mode fast-transient-response shunt regulator using CMOS technology

Chen

Kung

Hwang

2010

Analog Integr Circ Sig Process

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The demand for current-mode fast-transientresponse shunt regulator is increasing for the growth of portable electronics, such as cellular phones, PDA, laptops, etc. A new current-mode fast-transient-response shunt regulator is presented in this paper. The proposed shunt regulator used a single Miller compensation capacitor to increase stability. The current-mode shunt regulator helps the transient response to be faster than the voltage-mode low-dropout regulator (LDO) and the power noise (bounce noise) is smaller than one. The proposed current-mode shunt regulator has been fabricated with TSMC 0.35 lm 2P4M CMOS technology. The experimental results show the transient-response time is only 400 ns within 0.5% error and the maximum output voltage dip is only 70 mV for full loading current variation. Moreover, the line and load regulations are 26 lV/mA and 8 ppm/mA, respectively. The dropout current is 1.0741 mA for loading current 150 mA. The active chip area is 226 lm 9 310 lm.

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“…Because of the self-inductance of the off-chip bonding wires and the on-chip parasitic inductance inherent to the power rails, current surges cause voltage fluctuations in the on-chip power distribution network [8,9]. Traditionally, ground bounce has been a phenomenon associated with input/output buffers, internal digital circuitry, and clock gating [10,11,12,13,14]. Figure 2 shows the virtual power/ground rail clamp (VRC) scheme to dynamically reduce the supply voltage across a circuit during standby mode by interrupting he power supply and ground connections of the circuit [15].…”

Section: Introductionmentioning

confidence: 99%

Experimental measurement of a novel power gating structure with intermediate power saving mode

Kim¹,

Kosonocky

Knebel

et al. 2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 µm CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures.

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Estimation of ground bounce effects on CMOS circuits

Cited by 11 publications

References 6 publications

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

A new current-mode fast-transient-response shunt regulator using CMOS technology

Experimental measurement of a novel power gating structure with intermediate power saving mode

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