Estimation of average switching activity in combinational and sequential circuits

Ghosh,; Devadas,; Keutzer,; White,

doi:10.1109/dac.1992.227826

Cited by 323 publications

(178 citation statements)

References 7 publications

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“…In table 5, we present the relative error in the number of transitions after a logic simulation having used postlayout typical delays versus HSPICE simulation 1 . Generic conclusions are similar we did when we compared the results with the prelayout logic simulation ( Table 3).…”

Section: R E S U L T Smentioning

confidence: 99%

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Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

Baena

Juan-Chico

Bellido

et al. 2002

Lecture Notes in Computer Science

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Abstract. Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison between the evaluation of the switching activity calculated using logic (Verilog) and electrical (HSPICE) simulators. We also study how the variation on the delay model (min, typ, max) and parasitic effects affect the number of transitions in the circuit. Results show a variable and significant overestimation of this measurement using logic simulators even when including postlayout effects. Furthermore, we show the contribution of glitches to the overall switching activity, g iving that the treatment of glitches in conventional logic simulators is the main cause of switching activity overestimation.

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Section: R E S U L T Smentioning

confidence: 99%

“…Evaluating the switching activity in CMOS digital circuits is a key point to calculate its power consumption [1,2]. In mixed-signal circuits, switching activity of the digital part creates a switching noise that is transferred to the analog part [3,4,5].…”

Section: Introductionmentioning

confidence: 99%

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

Baena

Juan-Chico

Bellido

et al. 2002

Lecture Notes in Computer Science

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“…Ghosh [5] proposed to calculate signal activity performing an XOR at the output function at two consecutive times: a = P { y 0 ⊕ y T }. Probabilities and activities were computed using BDDs, but for large circuits, the method was unfeasible due to the BDD sizes.…”

Section: Fig 1 Effect Of Structural Dependences On Probability Compmentioning

confidence: 99%

Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level

Machado

Riesgo

Torroja

2009

Lecture Notes in Computer Science

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Abstract. This paper presents a partition method for probabilistic switching activity estimation of combinational circuits described at register transfer level (RTL). Probabilistic estimation of switching activity requires large and complex models that could be unfeasible for large circuits; therefore, circuit partitioning becomes a necessary step to address the analysis. Nevertheless, partition methods imply approximations that produce inaccurate results. We present a partition method based on disjoint signals that minimizes the error and, in addition, it is easy to carry out. Results show important reductions on the binary decision diagrams (BDD) of the probabilistic model as well as low errors. Furthermore, the BDD reduction ratio shows a tendency to increase with large circuits; whilst error seems to decrease with the circuit size.

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“…Examples of power estimation works that assume a zero delay model can be found in [2,10,16,17,21]. A few probabilistic and statistical methods for real delay power estimation have been presented in [5,12,19,22,18]. When characterizing modules for RT-level power estimation, the accuracy of the power estimate is important, making simulation approaches still beneficial.…”

Section: Related Workmentioning

confidence: 99%

A real delay switching activity simulator based on Petri net modeling

Murugavel¹,

Ranganathan²

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

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Estimation of average switching activity in combinational and sequential circuits

Cited by 323 publications

References 7 publications

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level

A real delay switching activity simulator based on Petri net modeling

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