ESD Simulation using Compact Models: from I/O Cell to Full Chip

Abstract

The modeling of ESD devices, such as II. ESD MOS MODELS MOS transistors, under ESD stress and bias conditions is reviewed. A practical macro-modeling approach A. On-Chip ESD Protection composed of industry standard BJT and MOS compact models is presented. SPICE-type circuit level ESD protection aims at shunting high current simulations that uses these models is demonstrated. discharges away from the core circuitry and to clamp pad These include examples at both the I/O cell as well as voltage to a safe level in order to avoid dielectric damage full-chip levels. Predicting ESD circuit performance as during the ESD event. A typical ESD protection scheme well as the inherent circuit simulation challenges are used in integrated circuits is shown in Fig.