ESD Protection Device and Circuit Design for Advanced CMOS Technologies

Semenov, O.; Sarbishaei, H.; Sachdev, Manoj

doi:10.1007/978-1-4020-8301-3

Cited by 67 publications

(42 citation statements)

References 2 publications

(2 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Complex ICs increasingly become susceptible to these failures owing to the scaling of technologies. Under the scaling regime, horizontal and vertical features are reduced in size which results in increasingly susceptibility to ESD/EOS failures [2]. These failures are caused by excessive electric field and/or excessive current densities and failure mechanisms include dielectric breakdown, electro-migration of metal lines and contacts [2].…”

Section: Introductionmentioning

confidence: 99%

“…Under the scaling regime, horizontal and vertical features are reduced in size which results in increasingly susceptibility to ESD/EOS failures [2]. These failures are caused by excessive electric field and/or excessive current densities and failure mechanisms include dielectric breakdown, electro-migration of metal lines and contacts [2]. ESD protection circuits consisting of I/O protection, and clamps are routinely used in ICs to protect them against ESD/EOS damages.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications

Elghazali

Sachdev

Opal

2014

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

Self Cite

View full text Add to dashboard Cite

Electrostatic discharge (ESD) and Electrical Overstress (EOS) are well-known problems in integrated circuits that affect the reliability, yield and cost. In addition, it has been reported that ESD/EOS contributes to significantly large fraction of failures [1]. It is important to design ESD protection circuits that are able to prevent these failures. In this work, a 65 nm hybrid ESD power supply clamp, which consists of static and transient clamps, for low leakage applications is presented. A diode configuration is used as a static clamp, while the transient clamp consists of a PMOS as the main transistor with body bias and thyristor as a delay element. Simulation and measurement results show that the clamp has fast response for ESD-like event.Extensive stability analysis demonstrates that the clamp is stable against false triggering, oscillation, power supply noise and latchup. Carried out measurement results also show that the clamp is capable of handling 1.55A of current while its leakage is only 32.9nA, whereas the traditional clamp has a leakage of 1.47µA.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications

Elghazali

Sachdev

Opal

2014

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…However, the GGNMOS needs a relatively large silicon area due to the low current passing capability. Therefore, significant parasitic effects are present, which makes GGNMOS devices the non-optimum solution for high-ESD robustness, high frequency, large pin count, and area-sensitive IC chips [2,3].…”

Section: Introductionmentioning

confidence: 99%

SCR-based ESD protection device with low trigger and high robustness for I/O clamp

Koo

Lee

2012

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a novel silicon controlled rectifier (SCR)-based ESD protection device with a low trigger voltage and high robustness for I/O clamp. The low trigger voltage is achieved by injecting the trigger current into main SCR. We measured the I-V characteristics, leakage current analysis and ESD robustness characteristics. The proposed ESD protection circuit was validated using a transmission line pulse (TLP) system. From the experimental results, the proposed ESD protection device has a lower trigger voltage of 5.6 V. Also, the robustness has measured to human body model (HBM) 8 kV and machine model (MM) 600 V. The proposed ESD protection device is designed in 0.35 um Bipolar-CMOS-DMOS (BCD) technologies.

show abstract

“…MOSFETs are widely used in switching devices, output drivers, and general ESD protection in high voltage ICs. However, when MOSFETs or MOSFET based devices are used as ESD protection devices, it has been found that MOSFETs are inherently weak with respect to ESD robustness and ESD reliability [2]. In addition, MOSFET based ESD protection devices consume a relatively large silicon area and latch-ups caused by static or transients may occur due to their relatively low holding voltage.…”

Section: Introductionmentioning

confidence: 99%

SCR stacking structure with high holding voltage for high voltage power clamp

Won

Jae-Pil²,

Koo³

2011

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:The latch-up immunity of high voltage power clamps used in high voltage ESD protection devices is rapidly becoming very important in high-voltage applications. The conventional high-voltage ESD devices are unsuitable for new high-voltage applications due to their low holding voltage, low ESD robustness, and their large size. In this study, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified using a 0.35 um BCD (Bipolar-CMOS-DMOS) process in order to achieve the desired holding voltage and an acceptable failure current. The experiment results show that the holding voltage of the stacking structure can exceed the operational voltage found in high-voltage applications. In addition, the stacking structure can provide a high ESD robustness.

show abstract

ESD Protection Device and Circuit Design for Advanced CMOS Technologies

Cited by 67 publications

References 2 publications

A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications

A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications

SCR-based ESD protection device with low trigger and high robustness for I/O clamp

SCR stacking structure with high holding voltage for high voltage power clamp

Contact Info

Product

Resources

About