ESD design automation for a 90nm ASIC design system

Brennan, Ciaran J.; Kozhaya, J.N.; Proctor, R.A.; Sloan, J.; Chang, Shunhua; Sundquist, James; Lowe, T.J.

doi:10.1109/eosesd.2004.5272614

Cited by 10 publications

(4 citation statements)

References 10 publications

(11 reference statements)

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“…Conclusions will be drawn regarding the effective ground wire resistance that can be considered during layout edition so as to be CDM protected. Inspired by other similar projects [22,26], several assumptions were made in order for this research's only focus to be on the ground net resistance impact on CDM protections:…”

Section: Proposed Structurementioning

confidence: 99%

“…While standardized field-induced CDM (FICDM) is the default CDM testing/stress method [12,23], transmission line pulsing (TLP) IV characterization reports have also been used for CDM purposes [17,23] Previous works show a variety of different methods to try to overcome the issues caused by CDM. Some findings argue the importance of the packaging on CDM occurrence (pin count, die area, metal frame structure [24]) by presenting their findings in terms of CDM peak currents dependence of various packages [18,23,27] or by trying to model the package parameters into software scripts to be used during pre-silicon testing simulation steps [15,20,26]. Similarly, a number of previously published works discuss the possibility of full-chip simulations [10,[16][17][18].…”

Section: Introductionmentioning

confidence: 99%

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CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Dobre

Coll²,

Brezeanu

2021

Electronics

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This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

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Section: Proposed Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Dobre

Coll²,

Brezeanu

2021

Electronics

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“…Devices directly connected to pins were included in the simulation netlist [8,9]. The substrate was neglected for the simulations.…”

Section: Investigation Of Parasitics Influencementioning

confidence: 99%

“…The authors propose a CDM simulation method to roughly predict the most probable CDM failure location for failure analysis. Brennan et al [9] introduced design tools for ensuring robust ESD protection in an early design stage. The authors demonstrate the applicability of the introduced tools for achieving high CDM robustness for test products in different technologies.…”

Section: Introductionmentioning

confidence: 99%