Equivalence of robust delay-fault and single stuck-fault test generation

A satisfiability-based test generator for path delay faults in combinational circuits

“…The percentage of the formula extraction time over the total test generation time is also included. As shown in the table, formula extraction (CNF) accounts for 10% of the total computation time on the average, compared to 63% reported in [16]. The formula extraction time can be reduced signi cantly, because the formula extraction needs to be performed only once for each cone and the necessary conditions to detect the path delay faults can be quickly determined and updated.…”

“…y a = 1). Overall, test generation for the fault d s-a-1 in the example circuit has been translated to the problem of nding a satisfying Table 1: Implication table for AND gate s0 s1 s0 s1 x0 x1 xx s0 s0 s0 s0 s0 s0 s0 s0 s1 s0 s1 s0 s1 x0 x1 xx s0 s0 s0 s0 s0 x0 s0 x0 s1 s0 s1 s0 s1 x0 s1 xx x0 s0 x0 x0 x0 x0 x0 x0 x1 s0 x1 s0 s1 x0 x1 xx xx s0 xx x0 xx x0 xx xx The technique described in [16] to generate a robust test for a path delay fault uses the above formulation to nd a test for an equivalent stuck-at fault in the modied circuit. The equivalent stuck-at fault is located on the I-edge of the target path P , which is either a primary input or the output of an inverter fed by a primary input.…”

“…The performance of the implementation described in [21] compares favorably to the best known structural algorithms. An extension of satis ability-based ATPG algorithms to generate robust tests for path delay faults has been reported in [16]. It was proven that a robust path delay fault in a circuit is detectable, if and only if an equivalent stuck-at fault is detectable in a modi ed circuit, which has at most four times the number of gates in the original circuit.…”

“…Conditions to detect a target path delay fault are r epresented b y a Boolean formula. Unlike the technique described in [16], which extracts the formula for each path delay fault, the proposed formulation needs to extract the formula only once for each circuit cone. Experimental results show tremendous time saving on formula extraction compared to other satis ability-based A TPG algorithms.…”

“…A test generator for path delay faults, however, may need to consider an exponential number of paths. Due to this fact, a large amount of time is spent on CNF formula extraction using the approach described in [16], thereby adversely a ecting the overall test generation time for circuits with a large number of paths. This paper describes a new CNF formulation for path delay faults that can be extracted much more e ciently, making it practical for circuits with a large number of paths.…”