Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell

Zerbe, J.; Werner, C.; Stojanović, Vladimir; Chen, F.; Wei, J.; Tsang, G.; Kim, D.; Stonecypher, W.F.; Ho, A.; Thrush, T.; Kollipara, Ravi; Horowitz, Mark; Donnelly, Kevin

doi:10.1109/jssc.2003.818572

Cited by 182 publications

(68 citation statements)

References 10 publications

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“…Additionally, the dielectric material of the transmission line causes loss. (2) where is the dielectric constant, tan is the loss tangent of the material, and is the speed of light. A thorough discussion of the skin and dielectric losses in modern materials is given 0018-9200/$20.00 © 2006 IEEE by Deutsch [14].…”

Section: Amplitude Pre-emphasismentioning

confidence: 99%

“…Since the transmitter operates from a fixed voltage supply, a maximum peak power limits the swing of the higher levels. One-tap amplitude pre-emphasis tends to provide some compensation for the frequency-dependent losses, however, more robust approaches use multiple taps to implement the transmit finite-impulse response (FIR) filter at the expense of additional power consumption [1], [2], [13].…”

Section: Amplitude Pre-emphasismentioning

confidence: 99%

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Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Buckwalter

Meghelli

Friedman

et al. 2006

IEEE J. Solid-State Circuits

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Abstract-A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase preemphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6 Gb/s and 600 mVpp output swing, a power budget of 3 mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24 mW, a budget of 4 mW/Gb/s.

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Section: Amplitude Pre-emphasismentioning

confidence: 99%

Section: Amplitude Pre-emphasismentioning

confidence: 99%

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Buckwalter

Meghelli

Friedman

et al. 2006

IEEE J. Solid-State Circuits

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“…As a result, if is sufficiently large compared to the marginal error probability , this observation alone is sufficient to guarantee that the proportion of codewords with two errors is increased compared to the independent-errors approximation. 4 In a similar manner, widening the error region to include deviations from the worst-case pattern by more than two symbols increases the probabilities of the corresponding higher-order error events.…”

Section: A Error Region Channel Signature and Error Correlationmentioning

confidence: 93%

“…The two main mechanisms that account for the most significant portion of the residual ISI in high-speed links are dispersion and reflection. In addition, residual interference may also include co-channel interference, caused, for instance, by electro-magnetic coupling (crosstalk) [3], [4]. As accounting for co-channel interference involves the same set of mathematical tools as accounting for the ISI, the remainder of the paper focuses on the effects of the ISI.…”

Section: System Modelmentioning

confidence: 99%

“…More formally, letting denote a lower bound on the proportion of symbol errors ascribed to the error region (e.g., 99% of all errors), the error region is the smallest possible interval of the form such that (4) where denotes the error event on the th symbol. The concept of error region is primarily useful when it is possible to pick large enough so that the ISI events in are responsible for the majority of the errors, and at the same time small enough so that every event in is likely to cause an error.…”

Section: A Error Region Channel Signature and Error Correlationmentioning

confidence: 99%

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Channel Coding For High-Speed Links: A Systematic Look at Code Performance and System Simulation

Blitvic

Lee²,

Stojanović

2009

IEEE Trans. Adv. Packag.

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Abstract-While channel coding is a standard method of improving a system's energy efficiency in digital communications, its practice does not extend to high-speed links. Increasing demands in network speeds are placing a large burden on the energy efficiency of high-speed links and render the benefit of channel coding for these systems a timely subject. The low error rates of interest and the presence of residual intersymbol interference (ISI) caused by hardware constraints impede the analysis and simulation of coded high-speed links. Focusing on the residual ISI and combined noise as the dominant error mechanisms, this paper analyzes error correlation through concepts of error region, channel signature, and correlation distance. This framework provides a deeper insight into joint error behaviors in high-speed links, extends the range of statistical simulation for coded high-speed links, and provides a case against the use of biased Monte Carlo methods in this setting. Finally, based on a hardware test bed, the performance of standard binary forward error correction and error detection schemes is evaluated, from which recommendations on coding for high-speed links are derived. Index Terms-Communication systems, integrated circuit interconnections, intersymbol interference (ISI).

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