Envelope-Tracking Two-Stage Power Amplifier With Dual-Mode Supply Modulator for LTE Applications

Kim, Jooseung; Kim, Dong–Su; Cho, Yunsung; Kang, Daehyun; Park, Byungjoon; Kim, Bumman

doi:10.1109/tmtt.2012.2225532

Cited by 63 publications

(29 citation statements)

References 20 publications

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“…A transistor-resizing technique for the PA to increase its efficiency is described in [24]. In [22] a two level linear amplifier supply is presented, a low bandwidth dynamic linear amplifier supply is explained in [26], and a multi-level linear amplifier supply is illustrated in [30]. An envelope shaping function to reduce nonlinear characteristics in the low supply voltage region is introduced in [20].…”

Section: Dissertation Outlinementioning

confidence: 99%

A High Slew-Rate Adaptive Biasing Hybrid Envelope Tracking Supply Modulator for LTE Applications

Yue

Bakkaloglu

2017

IEEE Trans. Microwave Theory Techn.

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As wireless communication enters smartphone era, more complicated communication technologies are being used to transmit higher data rate. Power amplifier (PA) has to work in back-off region, while this inevitably reduces battery life for cellphones.Various techniques have been reported to increase PA efficiency, such as envelope elimination and restoration (EER) and envelope tracking (ET). However, state of the art ET supply modulators failed to address high efficiency, high slew rate, and accurate tracking concurrently.In this dissertation, a linear-switch mode hybrid ET supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class-AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 V/µs to 93.4 V/µs and -87 V/µs to -152.5 V/µs respectively, dc gain from 45 dB to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power added efficiency (PAE) of 42.3% at 26.2 dBm for a 10 MHz 7.24 dB peak-to-average power ratio (PAPR) LTE signal and improves PAE by 8% at 6 dB back off from 26.2 dBm power amplifier (PA) output power with respect to fixed supply. With a 10 MHz 7.24 dB PAPR QPSK LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of -37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2 dBm PA output power, while with a 10 MHz 8.15 dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of -35.6 dBc and EVM of 6% at 26 dBm PA output power ii without digital pre-distortion (DPD). The proposed supply modulator core circuit occupies 1.1 mm 2 die area, and is fabricated in a 0.18 µm CMOS technology.iii To My Parents and Family iv ACKNOWLEDGMENTS

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Section: Dissertation Outlinementioning

confidence: 99%

A High Slew-Rate Adaptive Biasing Hybrid Envelope Tracking Supply Modulator for LTE Applications

Yue

Bakkaloglu

2017

IEEE Trans. Microwave Theory Techn.

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“…However, in the case of ignoring the output power level, the EER system has very low gain in lowpower regions due to the influence of the saturated operation of switching PA and the constant-envelope phase-modulated RF input signal [8]. Meanwhile, the envelope tracking (ET) PA, another popular efficiency enhancement technique, has been proposed in [8][9][10][11][12][13][14][15]. The technique modulates the supply voltage of the PA according to the input power level to reduce the dc power consumption at low power, but typically suffers from a complex system and a sophisticated supply modulator [10].…”

Section: Introductionmentioning

confidence: 99%

A Low-Power CMOS Class-E Chireix RF Outphasing Power Amplifier for WLAN Applications

Zhu

2016

Wireless Pers Commun

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This paper describes the design and implementation of a low-power CMOS class-E Chireix RF outphasing power amplifier (PA) for WLAN applications. The proposed circuit is based on cascode class-E topology with two-stage structure and Chireix power combiner with a floating load. This class-E topology adopts self-biased technique and current-reused technique that avoids using thick-oxide transistors and can enhance the driving ability and power gain. Additionally, the Chireix combiner can reduce the loss of power and improve the efficiency by avoiding the use of isolation resistance. With a 2.5 V power supply, the realized prototype achieved 21.4 dBm of maximum output power and 29.9 % of average power-added efficiency (PAE) at 2.4 GHz. When operated for minimum input levels at 2.5 V, it reached 38.8 dB power gain. For a WLAN OFDM signal with 20 MHz, the error vector magnitude of 3 % is achieved with peak drain efficiency of 62 %. Moreover, the outphasing power amplifier is fully integrated with TSMC 0.18-lm CMOS technology and the chip area including testing pads is 1.07 9 1.17 mm 2 .

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“…Low drop-out regulators and switching regulators are not good choice for the bias modulator due to low efficiency and narrow bandwidth, respectively [3,4]. The hybrid bias modulators, which have a highly efficient switching stage and a broadband linear stage, have been popular for the ET applications [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. The switching stage supplies most of the current which are around very low frequency including DC.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the bias modulators, which are generally designed using CMOS process, have been generally applied to those PAs using GaAs HBT or SiGe BiCMOS processes for higher performance [13][14][15][16][17][18][19][20]. However, the PAs based on CMOS process has great advantages in lower cost and higher integration in spite of its relatively poor performances [23][24][25].…”

Section: Introductionmentioning

confidence: 99%

A CMOS Envelope Tracking Power Amplifier for LTE Mobile Applications

Ham¹,

Jung²,

Kim³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

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Envelope-Tracking Two-Stage Power Amplifier With Dual-Mode Supply Modulator for LTE Applications

Cited by 63 publications

References 20 publications

A High Slew-Rate Adaptive Biasing Hybrid Envelope Tracking Supply Modulator for LTE Applications

A High Slew-Rate Adaptive Biasing Hybrid Envelope Tracking Supply Modulator for LTE Applications

A Low-Power CMOS Class-E Chireix RF Outphasing Power Amplifier for WLAN Applications

A CMOS Envelope Tracking Power Amplifier for LTE Mobile Applications

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