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A quarter-wavelength impedance transformer as well as a number of other factors limit the bandwidth (BW) of Doherty power amplifiers (PAs). We utilize the lower Q of a quarter-wavelength transformer and propose a phase compensation circuit and an additional offset line to be incorporated into the matching networks for an enhanced BW of the Doherty PA. The quarter-wavelength transformer and the final output circuit have the same . Input dividing networks are also analyzed for operation of broad BW. The Doherty PA for long term evolution (LTE) applications is integrated into a 1.4 1.4 mm 2 die using an InGaP/GaAs heterojunction bipolar transistor (HBT) process. For an LTE signal with a 7.5-dB peak-to-average power ratio (PAPR) and a 10-MHz BW, the PA with a supply voltage of 4.5 V delivers a power-added efficiency (PAE) of 36.3% and an adjacent channel leakage ratio (ACLR) of 32 dBc with an average output power of 27.5 dBm at a frequency of 1.85 GHz. Across frequencies from 1.6-2.1 GHz, the PA performs with a PAE of more than 30%, a gain of more than 28 dB and an ACLR of less than 31 dBc at an average output power of 27.5 dBm while satisfying the standard spectrum mask. These figures verify that the proposed bandwidth enhancement techniques are effective for handset Doherty PAs.

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An envelope-tracking (ET) CMOS power amplifier (PA) is fabricated using a 0.18-m CMOS process. The module containing the supply modulator, the PA, and the output transformer is implemented on a printed circuit board (PCB). The CMOS PA employs the second and third harmonic controls at the input and the second harmonic short at the output for improved linearity. The impact on the nonlinearity of the cascode differential structure is studied and optimized. A proposed output transformer on the PCB minimizes the loss and enhances the efficiency of the PA. The ET on the gate of the common gate transistor is proposed to achieve high linearity and efficiency without using a digital pre-distortion technique. For a long-term evolution (LTE) signal at 1.85 GHz with a 10-MHz bandwidth and a 16QAM 7.5-dB peak-to-average power ratio, the ET CMOS PA module achieves a power-added efficiency of 34%, an error vector magnitude of 2.8%, and an adjacent channel leakage ratio of 34.2 dBc at an average output power of 26 dBm. The ET operation reduces the total current consumption by 10% to 34%, according to the power level, over that of the standalone PA for the LTE signal.Index Terms-CMOS, efficient, envelope tracking (ET), linear, handset, power amplifier (PA), long-term evolution (LTE).