Enhancing Microprocessor Immunity to Power Supply Noise With Clock-Data Compensation

Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement

“…The effect of noise on timing, however, has been reported in few works [5], [6] and other works have been investigated through simulation [4], [7]. studied transition waveform distortion due to sharp voltage spike.…”

“…studied transition waveform distortion due to sharp voltage spike. Reference [6] discusses impact of power noise on clock signal. Reference [5] is a primary version of this work.…”

Globally integrated power and clock distribution network

“…In [14], clock and power distribution networks are considered simultaneously to enhance the immunity to power supply noise. However, no research on utilizing the same global network for both power and clock distribution has been described in the literature.…”

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

“…This supply noise significantly affects the electrical characteristics of clock buffers [1]. The effect of power supply noise on 2-D clock distribution networks has been investigated in [11]- [13]. The effect of power supply noise on 3-D clock distribution networks, however, has not been adequately explored.…”

“…The jitter produced in 1063-8210 © 2013 IEEE clock distribution networks is mainly due to the power supply noise on the clock buffers [18]. The effect of the power supply noise on period jitter in 2-D ICs is analyzed in [11] and [13], while to the best of authors' knowledge, this paper discusses period jitter in 3-D ICs for the first time.…”