Enhanced Via Integration Process for Copper/Ultralow- $k$ Interconnects

Graphene Capping of Cu Back-End-of-Line Interconnects Reduces Resistance and Improves Electromigration Lifetime

“…Scaling of the BEOL is important to reduce the resistive-capacitive delay and improve the computation speed. Cu has been used as the main fill metal in BEOL structures owing to its lower resistivity (1.6 μΩ-cm) compared to other metals. , As the feature size of the Cu line decreases, reducing the resistance while maintaining reliability becomes increasingly difficult because of electromigration (EM) and time-dependent dielectric breakdown of Cu interconnects. When the line dimensions decrease to several tens of nanometers, which is less than the electron mean free path (39.9 nm) of Cu, electron scattering at the surface and grain boundary increases, leading to an exponential increase in Cu resistivity. − In addition, the amount of current-induced heat is higher in smaller Cu lines, boosting the EM.…”

32nm Node Highly Reliable Cu/Low-k Integration Technology with CuMn Alloy Seed

“…Before capping, in the presence of O, some amount of Mn might segregate at Cu grain boundaries or in Cu grains, preventing Cu recrystallization properly and eventually resulting in many crystal defects such as vacancies in the Cu plate. The stress at PBV structures at a temperature of 225 °C was usually higher than nominal structures [6]. The stress caused vacancy movement and nucleation under the via, resulting in via open fail as voids grew rapidly.…”

“…As Nogami [2] pointed out a robust non-oxidized liner is needed to isolate Mn from O-rich area: Intral Level Dielectrics (ILD). A conventional gouging liner process forming enhanced via-line contact is commonly used in Cu/ low-k (k>=3.0) integration to achieve good wiring reliability [3][4][5][6]. A similar gouging liner process was adopted at the early development phase of the 32nm node.…”

Rapid laser-induced photochemical conversion of sol–gel precursors to In2O3 layers and their application in thin-film transistors

“…In addition, deposition of semiconducting metal oxides by "sol-gel" has so far been limited to high processing temperatures, typically in excess of >350 °C, rendering the technology incompatible with inexpensive, temperature-sensitive substrates such as plastic, the material of choice for large-scale roll-toroll (R2R) processes. [7][8][9] This post-deposition heat treatment is a major obstacle that hinders the integration of heat-sensitive flexible polymeric substrates. Therefore, it is essential to develop alternative methods of processing that can meet the demands relevant to this area.…”

“…Lowfluence/multiple-pulse LA with XeCl excimer laser (308 nm) was suggested by Yang et al in the fabrication of IGZO TFTs resulting in a field-effect mobility of 7.65 cm 2 /Vs. 8 A different approach was recommended by Tsay et al where the researchers employed high fluence and a low number of pulses (15) from a KrF excimer laser (248 nm) for improving the physical properties of IGZO thin film. 17 In 2 O 3 is a wide band-gap semiconducting material with great perspectives in the transparent electronics technology as it exhibits both high optical transparency and superior electronic properties with electron mobility of up to 220 cm 2 /Vs reported for single crystals.…”