Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme

Yu, Jintao; Nguyen, Hoang Anh Du; Lebdeh, Muath Abu; Taouil, Mottaqiallah; Hamdioui, Said

doi:10.1109/nanoarch47378.2019.181296

Cited by 10 publications

(11 citation statements)

References 29 publications

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“…In this context, an enhanced scouting logic scheme was proposed in Reference [26], but it used a more complex 1T1R array to achieve higher reliability of logic operations. In the same direction, inspired by the crossbar interface circuit proposed by Papandroulidakis et al in Reference [27], here we designed and evaluated the performance of an alternative and more flexibly parameterizable circuit implementation for the voltage-based SA, which can lead to a more robust behavior against HRS and LRS variability.…”

Section: Sensing Circuit Implementations That Enable Memristor-based Logic Operationsmentioning

confidence: 99%

Robust Circuit and System Design for General-Purpose Computational Resistive Memories

Pinto¹,

Vourkas²

2021

Electronics

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Resistive switching devices (memristors) constitute a promising device technology that has emerged for the development of future energy-efficient general-purpose computational memories. Research has been done both at device and circuit level for the realization of primitive logic operations with memristors. Likewise, important efforts are placed on the development of logic synthesis algorithms for resistive RAM (ReRAM)-based computing. However, system-level design of computational memories has not been given significant consideration, and developing arithmetic logic unit (ALU) functionality entirely using ReRAM-based word-wise arithmetic operations remains a challenging task. In this context, we present our results in circuit- and system-level design, towards implementing a ReRAM-based general-purpose computational memory with ALU functionality. We built upon the 1T1R crossbar topology and adopted a logic design style in which all computations are equivalent to modified memory read operations for higher reliability, performed either in a word-wise or bit-wise manner, owing to an enhanced peripheral circuitry. Moreover, we present the concept of a segmented ReRAM architecture with functional and topological features that benefit flexibility of data movement and improve latency of multi-level (sequential) in-memory computations. Robust system functionality is validated via LTspice circuit simulations for an n-bit word-wise binary adder, showing promising performance features compared to other state-of-the-art implementations.

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Section: Sensing Circuit Implementations That Enable Memristor-based Logic Operationsmentioning

confidence: 99%

Robust Circuit and System Design for General-Purpose Computational Resistive Memories

Pinto¹,

Vourkas²

2021

Electronics

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“…5b shows how the reading devices should be configured during the AND operation in order to reduce the impact of the variations; the equivalent resistance of two read elements being both in logic 1 will be R L + R L = 2R L while it will be R L + R H ≈ R H when reading two elements one in logic 1 and one in logic 0. This solution is known as Enhanced Scouting Logic (ESL) [42]. The implementation of ESL as shown in Fig.…”

Section: A Bitwise Logical Operationsmentioning

confidence: 99%

“…• Materials/Technology: At these stage, there are still many open questions and aspects where the technology can help in making memristive device based computing a reality. Examples are device endurance [8], high resistance ratio between the off and on state of the devices [42], multilevel storage, precision of analog weight representation, resistance drift, inherent device-to-device and cycle-tocycle variations, yield issues, etc. • Circuit/Architecture: Analog Computation-in-Memory comes with new challenges to the design of peripheral circuits.…”

Section: Potential and Challengesmentioning

confidence: 99%

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The Power of Computation-in-Memory Based on Memristive Devices

Lebdeh

Nguyen

et al. 2020

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Conventional computing architectures and the CMOS technology that they are based on are facing major challenges such as the memory bottleneck making the memory access for data transfer a major killer of energy and performance. Computation-in-memory (CIM) paradigm is seen as a potential alternative that could alleviate such problems by adding computational resources to the memory, and significantly reducing the communication. Memristive devices are promising enablers of a such CIM paradigm, as they are able to support both storage and computing. This paper shows the power of memristive device based CIM paradigm in enabling new efficient applicationspecific architectures as well as efficient implementations of some known domain-specific architectures. In addition, the paper discusses the potential applications that could benefit from such paradigm and highlights the major challenges.

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“…Developing LIM hardware accelerators would enable the deployment at the edge of powerful and data-intensive computing paradigms such as binarized neural networks (BNNs) [5][6][7] and hyperdimensional computing [8][9][10], which strongly rely on the energy-efficient execution of logic operations. Among LIM solutions [11][12][13][14][15][16][17], circuits based on resistive memory (RRAM) technology and the implication logic (IMPLY) offer ultra-dense back end of line (BEOL) integration. Currently, the main showstoppers [12,18] hindering the introduction of RRAM-based LIM circuits are the high energy per operation (as compared to CMOS gates), the degradation of the logic values of RRAMs during circuit operation, and the need to apply very precise voltage pulses (mV accuracy may be required [12,18,19]).…”

Section: Introductionmentioning

confidence: 99%

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing

Zanotti¹,

Pavan²,

Puglisi³

2021

Micromachines

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Logic-in-memory (LIM) circuits based on the material implication logic (IMPLY) and resistive random access memory (RRAM) technologies are a candidate solution for the development of ultra-low power non-von Neumann computing architectures. Such architectures could enable the energy-efficient implementation of hardware accelerators for novel edge computing paradigms such as binarized neural networks (BNNs) which rely on the execution of logic operations. In this work, we present the multi-input IMPLY operation implemented on a recently developed smart IMPLY architecture, SIMPLY, which improves the circuit reliability, reduces energy consumption, and breaks the strict design trade-offs of conventional architectures. We show that the generalization of the typical logic schemes used in LIM circuits to multi-input operations strongly reduces the execution time of complex functions needed for BNNs inference tasks (e.g., the 1-bit Full Addition, XNOR, Popcount). The performance of four different RRAM technologies is compared using circuit simulations leveraging a physics-based RRAM compact model. The proposed solution approaches the performance of its CMOS equivalent while bypassing the von Neumann bottleneck, which gives a huge improvement in bit error rate (by a factor of at least 108) and energy-delay product (projected up to a factor of 1010).

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Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme

Cited by 10 publications

References 29 publications

Robust Circuit and System Design for General-Purpose Computational Resistive Memories

Robust Circuit and System Design for General-Purpose Computational Resistive Memories

The Power of Computation-in-Memory Based on Memristive Devices

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing

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