Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs

Rim, K.; Welser, J.J.; Hoyt, Judy L.; Gibbons, J. F.

doi:10.1109/iedm.1995.499251

Cited by 99 publications

(59 citation statements)

References 8 publications

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“…For a Ge content of 30% in the underlying relaxed Si Ge , the electron mobility in the strained Si is enhanced by roughly 80%. A hole mobility enhancement of similar magnitude has been reported for surface-channel strained-Si p-MOSFET's [8]. These surfacechannel strained-Si n-and p-MOSFET's are identical to conventional Si MOSFET's in their operation principle, and are expected to retain all the advantages of surface-channel (as op- posed to buried-channel) devices, including excellent current drive/turn-off characteristics, and scaling behavior.…”

supporting

confidence: 56%

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Rim

Hoyt

Gibbons

2000

IEEE Trans. Electron Devices

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346

134

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Abstract-Deep submicron strained-Si n-MOSFET's were fabricated on strained Si/relaxed Si 0 8 Ge 0 2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFET's exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.

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supporting

confidence: 56%

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Rim

Hoyt

Gibbons

2000

IEEE Trans. Electron Devices

Self Cite

346

134

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“…• Bulk strained Si (the analogue of today's Si CMOS P -/P + epi substrates) -bulk strained Si substrates comprise an epitaxial strained Si film on top of a uniform content, SiGe layer, whose lattice constant is engineered by a compositionally graded SiGe layer [35][36][37][38].…”

Section: Intrinsic Materials Configurationsmentioning

confidence: 99%

“…This approach was utilized in the fabrication of the first enhanced mobility NMOSFET in 1994 [36]. Similarly, an enhanced mobility PMOSFET was fabricated in 1995 [37] (see also reference two in [37]), but this required a more complex configuration with a dual channel heterostructure that consisted of strained Si on top of strained Si 1-y Ge y that was deposited on a relaxed Si 1-x Ge x layer, y < x [43]. This methodology was utilized since the alternative of having just a single strained Si layer would have required a very large Ge content (≥40%) for a mobility enhancement of ≥ 2.5 [10,15,45].…”

Section: Bulk Strained Silicon and Soi Configurationsmentioning

confidence: 99%

Starting Materials and Functional Layers for The 2005 International Technology Roadmap for Semiconductors: Challenges and Opportunities

Huff¹,

Myers²,

Walden³

et al. 2005

AIP Conference Proceedings

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Abstract. The integrated circuit (IC) industry is in the midst of an explosive expansion of new materials, processes and tools utilized in the fabrication of ICs and, accordingly, there are a host of associated new challenges and opportunities. These include, for example, the implementation of 300mm diameter wafers, the drive to equivalent oxide thickness in the sub-1.0 nanometer regime for high-performance logic devices via high-k gate-dielectric materials and metal gate electrodes, strained silicon methodologies, the expanded utilization of silicon-on-insulator (SOI) materials, copper metallization, low-k inter-level dielectrics and a plethora of alternative transistor configurations in non-classical CMOS device structures. We will discuss the implications of these advanced materials and device configurations on the International Technology Roadmap for Semiconductors (ITRS).

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“…For transistors, the carrier mobility in the channel region has continuously increased by inducing strain either biaxially or uniaxially [1][2][3][4][5]. In 2003, Intel introduced 90 nm technology node and at that time, nano-electronics received its fundaments [1].…”

Section: Introductionmentioning

confidence: 99%

“…Stressor materials e.g. Si 1-x Ge x (or Si 1-y C y ) has been deposited selectively in the source/ drain regions using chemical vapor deposition (CVD) [1][2][3][4][5]. In order to solve the difficulties in the growth, an absolute understanding of its reaction mechanism, kinetics and thermodynamics is required.…”

Section: Introductionmentioning

confidence: 99%