Engineering of the spin on dopant process on silicon on insulator substrate

Abstract

We report on a systematic analysis of phosphorus diffusion in silicon on insulator thin film via spin-on-dopant process (SOD). This method is used to provide an impurity source for semiconductor junction fabrication. The dopant is first spread into the substrate via SOD and then diffused by a rapid thermal annealing process. The dopant concentration and electron mobility were characterized at room and low temperature by four-probe and Hall bar electrical measurements. Time-of-flight-secondary ion mass spectroscopy was performed to estimate the diffusion profile of phosphorus for different annealing treatments. We find that a high phosphorous concentration (greater than 1020 atoms cm−3) with a limited diffusion of other chemical species and allowing to tune the electrical properties via annealing at high temperature for short time. The ease of implementation of the process, the low cost of the technique, the possibility to dope selectively and the uniform doping manufactured with statistical process control show that the methodology applied is very promising as an alternative to the conventional doping methods for the implementation of optoelectronic devices.

Stochastic Assessment of Dissolution at Fluid‐Mineral Interfaces

“…The positive resist AZ 5214E is then spin‐coated in two different steps (at 750 rpm for 5 s and at 4,000 rpm for 40 s) and finally annealed at 120°C for 2 min. After the optical lithography and the corresponding developing step in tetramethylammonium hydroxide solution for 50 s, the sample is loaded in the electron beam evaporation chamber for titanium deposition (Barri et al., 2020). The final Ti thickness is about 40 ± 1 nm (datum confirmed by AFM analysis).…”

Fully Integrated Silicon Photonic Erbium-Doped Nanodiode for Few Photon Emission at Telecom Wavelengths

“…Finally, a lift-off is performed to remove the resist. The titanium layer is introduced before the gold contact to improve the gold adhesion on silicon ( Figure 1 d) [ 24 ].…”

Electrical Noise Analysis of Z Shape Horizontal Pocket and Hetero Stack TFETs under Trap Distribution

“…Once the device area is defined, then photo masking with lithography 7 is used to deposit the n and p type dopants of uniform mode into the source and drain regions of the device through Spin-on-dopant (SOD) process. 4 In this technique, dopant is first spread into the substrate through (SOD) and then diffusion takes place by rapid thermal annealing process. This process of doping is found very promising for ease of implementation, cost terms, lesser crystal damage and uniform doping respectively.…”

“…Despite its many advantages, continuous MOSFET downscaling has various limitations, including a subthreshold swing (SS) limit of 60 mV/ decade, serious power dissipation, higher conduction losses, and massive short-channel effects (SCEs). [1][2][3] Tunnel field-effect transistors (TFETs) [4][5][6][7][8][9] have been proposed as a possible MOSFET replacement and a basis for future semiconductor technologies. TFETs possess unique characteristics that make them ideal for various applications, such as low-power, analog/RF, and optosensing devices.…”