2012 International Electron Devices Meeting 2012
DOI: 10.1109/iedm.2012.6479143
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Engineering grains of Ge<inf>2</inf>Sb<inf>2</inf>Te<inf>5</inf> for realizing fast-speed, low-power, and low-drift phase-change memories with further multilevel capabilities

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Cited by 13 publications
(10 citation statements)
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“…Wang et. al 8 experimentally showed a trend of decreased reset and set times as radii decreased from 8.5 nm to 5 nm but achieved sub-nanosecond reset while requiring ~50 ns for set. The longer reset and shorter set times in our simulations are consistent with a v∞ that underestimates melting velocities but overestimates crystallization velocities, resulting in less melting during reset, more crystallization while cooling after reset, and faster crystallization during set.…”
mentioning
confidence: 98%
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“…Wang et. al 8 experimentally showed a trend of decreased reset and set times as radii decreased from 8.5 nm to 5 nm but achieved sub-nanosecond reset while requiring ~50 ns for set. The longer reset and shorter set times in our simulations are consistent with a v∞ that underestimates melting velocities but overestimates crystallization velocities, resulting in less melting during reset, more crystallization while cooling after reset, and faster crystallization during set.…”
mentioning
confidence: 98%
“…We model temperature and grain size dependent phase change velocities in Ge2Sb2Te5 (GST), a common phase change material, based on kinetic and thermodynamic parameters. We incorporate heterogeneous melting into a finite element phase change model coupled with electrothermal physics [2][3][4][5][6][7] and show that it can account for the experimentally demonstrated PCM performance improvement with decreasing grain size 8,9 .…”
mentioning
confidence: 99%
“…(II) Initialization electrical pulse : a weak incubation voltage pulse (~0.3 V at 10 ns) on GST can help to pre-form fourfold membered atomic rings, which are the precursors for distorted octahedrons in rocksalt c-GST 5 6 . (III) Diminishing grain size : as the grain size of the GST is reduced from 17 to 13 nm, the Set time can be reduced from 44 to 40 ns 7 8 . In contrast, reducing the Reset power can not only prolong PCM cell life to compete with DRAM (>10 15 cycles) 3 , but can also effectively lower the standards for drive capability of gating device to achieve high-density integration 9 10 .…”
mentioning
confidence: 99%
“…The suppressed peaks and the smaller grain size could be indicated the incorporated W atom plays a role in suppressing crystallization of the Sb 3 Te films, which correspond to the increased T c and E a of W x Sb 3 Te films. In practical applications, the smaller grain could reduce the power consumption of the cell device [17].…”
Section: Methodsmentioning
confidence: 99%