Engine for characterization of defects, overlay, and critical dimension control for double exposure processes for advanced logic nodes

Holmes, Steven J.; Koay, Chiew-Seng; Petrillo, Karen; Chen, Kuang‐Jung; Colburn, Matthew; Cantone, Jason; Ueda, K.; Metz, Andrew; Dunn, Shannon; Dommelen, Youri van; Crouse, Michael; Galloway, Judy; Schmitt-Weaver, Emil; Jiang, Aiquin; Routh, Robert; Tang, Cherry; Slezak, Mark; Kini, Sumanth; DiBiase, Tony

doi:10.1117/12.828483

Cited by 5 publications

(2 citation statements)

References 11 publications

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“…Previously published results have shown overlay on resolution for the chemical freeze process to be between 6 and 7 nm on ASML 1700i TWINSCAN™ scanner using the traditional 10-parameter process corrections and ASML ASCAL™ lens heating calibration 9 . The thermal freeze process is capable of better, effective overlay than the chemical freeze, due to its improved line CDU and reduced line growth as discussed above.…”

Section: Overlay On Resolutionmentioning

confidence: 97%

Evaluation of double-patterning techniques for advanced logic nodes

et al. 2010

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The development of Double-Patterning (DP) techniques continues to push forward aiming to extend the immersion based lithography below 36 nm half pitch. There are widespread efforts to make DP viable for further scaling of semiconductor devices. We have developed Develop/Etch/Develop/Etch (DE2) and Double-Expose-Track-Optimized (DETO) techniques for producing pitch-split patterns capable of supporting semiconductor devices for the 16 nm and 11 nm nodes. The IBM Alliance has established a DETO baseline, in collaboration with ASML, TEL, CNSE, and KLATencor, to evaluate the manufacturability of DETO by using commercially available resist systems. Presented in this paper are the long-term performance results of these systems relevant to defectivity, overlay, and CD uniformity.

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Section: Overlay On Resolutionmentioning

confidence: 97%

Evaluation of double-patterning techniques for advanced logic nodes

et al. 2010

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“…Version 3 additionally develops each exposed layer right after each exposure and post-exposure bake step essentially implementing conventional double-patterning techniques [9][10][11]. It has to be pointed out that for both, version 1 as well as version 2,…”

Section: Lithographymentioning

confidence: 99%

Fabrication of dual damascene BEOL structures using a multilevel multiple exposure (MLME) scheme, part 2: RIE-based pattern transfer and completion of dual damascene process yielding an electrically functional via chain

Harrer¹,

Arnold²,

Goldfarb

et al. 2010

SPIE Proceedings

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A novel back-end-of-line (BEOL) patterning and integration process termed Multi-Level Multiple Exposure (MLME) technique is herein introduced. The MLME technique simplifies BEOL dual damascene (DD) integration while simultaneously being applicable to all BEOL levels. It offers a patterning resolution reaching into the sub-100nm region and improves semiconductor manufacturing cost and throughput. MLME employs a dual-layer imaging stack (via + trench resists) cast onto a customized etch transfer multilayer stack. This process implements a strict litho-litho-etch sequence for transferring the trench-and via-patterns into the dielectric layer. Under the MLME scheme, two imaging steps (i.e. via-and trench-level patterning) are executed consecutively followed by a dry etch process that transfers the lithographically-formed patterns into the customized etch transfer multilayer stack and further into the dielectric layer. The MLME integration scheme not only decreases the number of overall process steps for the full DD BEOL process but also eliminates several inter-tool wafer exchange sequences as performed in a conventional litho-etch-litho-etch process flow. All MLME process steps were demonstrated i.e. combined 193nm-dry dual-resist layer MLME via-and trenchlithography, full pattern transfer of via-and trench-patterns into the dielectric layer using reactive ion etching (RIE), as well as electroplating and polishing of the DD patterns. This paper provides a detailed description of both postlithography steps of the DD process for a DD BEOL structure, i.e. (i) the RIE-pattern transfer process with the customized multilayer stack, and (ii) the metallization process completing the DD process for one BEOL layer. Furthermore, the integration capabilities of the MLME technique were demonstrated and characterized by generating an electrically functional via-chain connecting two neighboring BEOL layers fabricated by subsequently applying the MLME approach to both layers. An exhaustive description and evaluation of MLME lithographic patterning is given in an accompanying paper [1].

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