Energy-efficient, fast-settling, modified nested-current-mirror, single-stage-amplifier for high-resolution LCDs in 90-nm CMOS

Dadashi, Ali; Berg, Y.; Mirmotahari, Omid

doi:10.1007/s10470-018-1220-7

Cited by 3 publications

(3 citation statements)

References 88 publications

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“…The right-half plane (RHP) zero associated with the Miller capacitance, together with the necessity of additional capacitors for compensating the inner gain stages of NMC amplifier, however, reduces its maximum bandwidth and leads to poor performance metrics [26]. Many variants of NMC amplifier have thus been proposed [27]- [33], along with some solutions for eliminating the Miller compensation capacitors altogether [20], [34], [35]. Despite looking attractive for a multistage amplifier, removing the Miller capacitors comes with degraded power efficiency, since extra feedback loops and more biasing current would be required to compensate the inner gain-stages.…”

Section: Introductionmentioning

confidence: 99%

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

2022

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This paper proposes an optimal design approach for three-stage amplifiers driving an ultra-wide range of load capacitor. To this end, efficient state-of-the-art solutions have been combined to develop a power-efficient frequency compensation solution. High-speed feedback pathways relying on Miller capacitors and current buffers are implemented within the amplifier scheme to push the non-dominant poles to high frequencies for small to medium load capacitors. A small resistor is also shared between the two pathways to improve the stability regardless of the load capacitor. A serial R-C branch is then added to extend the lower limit of load drive capability to small load capacitors. Gain margin is, for the first time in literature, analytically evaluated and included in the design phase. A prototype of the proposed amplifier is fabricated in 65-nm CMOS process with active area of 0.0017 mm 2 and 1.15 pF total compensation capacitance. It can drive the load capacitor range from 200 pF to 100 nF, while drawing a quiescent current of 7.4 µA from a 1.2-V input voltage supply. A unity-gain frequency of 1.67 MHz was measured with an average slew-rate of 1.31 V/µs, when the proposed amplifier is wired in unity-gain configuration to drive a 500-pF load capacitor.

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Section: Introductionmentioning

confidence: 99%

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

2022

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“…This approach, however, leads to an explosion of design time and complexity of the LCD driver. A generic amplifier topology with enough stability margin over the entire C L range is, evidently, more attractive for such application …”

Section: Introductionmentioning

confidence: 99%

“…A generic amplifier topology with enough stability margin over the entire C L range is, evidently, more attractive for such application. 1,2,4,13,14 High-gain multistage amplifiers are preferred over single-stage configurations in modern mixed-signal processing modules with stringent accuracy requirement. These amplifiers ensure that maximum signal dynamic range is achieved under the low-voltage supply of short-channel metal-oxide semiconductor (MOS) transistors since the output stage can be implemented by two transistors only.…”

Section: Introductionmentioning

confidence: 99%

Global impedance attenuation network for multistage OTAs driving a broad range of load capacitor

Aminzadeh

Valinezhad

Grasso

2020

Circuit Theory & Apps

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Summary Advanced multistage amplifiers suffer from load‐dependent stability issues, which limit the load capacitor range they can drive. In this work, the concept of global impedance attenuation (GIA) network is introduced to improve an amplifier's stability in the presence of significant load capacitor variations. Composed of multiple parallel resistor‐capacitor (RC) branches, the equivalent high‐frequency output impedance of gain stages is shaped by the GIA network such that a desired frequency spectrum is obtained over a wide range of load capacitor. The parasitic poles at the output of the gain stages are nullified by the proposed network, thereby simplifying the amplifier's transfer function and reducing the minimum load capacitor it can drive. The idea is applied to design a three‐stage operational transconductance amplifier (OTA) with cascode global impedance attenuation (CGIA). Small‐signal analysis shows that the OTA is stable regardless of the load capacitor, and it can drive very small to ultra‐large load capacitors. This feature is verified by the post‐layout simulations of a CGIA amplifier in 0.18‐μm complementary metal‐oxide semiconductor (CMOS) process. The core occupies a die area of 0.0053 mm2 while consuming a static current of 10.97 μA from 1.8‐V voltage supply. The unity‐feedback configuration is unconditionally stable for any load capacitor higher than 10 pF. To the best of our knowledge, this corresponds to the widest range of load capacitance reported for prior‐art three‐stage amplifiers.

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Power-Scaling Output-Compensated Three-Stage OTAs for Wide Load Range Applications

Riad

Estrada-López

Padilla-Cantoya

et al. 2020

IEEE Trans. Circuits Syst. I

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Energy-efficient, fast-settling, modified nested-current-mirror, single-stage-amplifier for high-resolution LCDs in 90-nm CMOS

Cited by 3 publications

References 88 publications

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

Global impedance attenuation network for multistage OTAs driving a broad range of load capacitor

Power-Scaling Output-Compensated Three-Stage OTAs for Wide Load Range Applications

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